ST72321B STMICROELECTRONICS [STMicroelectronics], ST72321B Datasheet - Page 155

• Manufacturer Part Number: ST72321B
• Description: 64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V
Figure 78. Unused I/Os configured as input
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
tion. A positive injection is induced by V
on page 139
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see
peak current value taken at a fixed V
production. This value depends on V
5. The R
scribed in
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
ΣI
I
Symbol
INJ(PIN)
t
t
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
INJ(PIN)
t
greater EMC robustness and lower cost.
r(IO)out
f(IO)out
w(IT)in
V
R
C
V
V
I
I
hys
PU
S
IH
L
IO
IL
3)
PU
3)
Figure
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Injected Current on PC6 (Flash de-
vices only)
Injected Current on an I/O pin
Total injected current (sum of all I/O
and control pins)
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
I/O pin capacitance
Output high to low level fall time
Output low to high level rise time
External interrupt pulse time
pull-up equivalent resistor is based on a resistive transistor (corresponding I
for more details.
79).
V
DD
Parameter
10kΩ
10kΩ
1)
UNUSED I/O PORT
UNUSED I/O PORT
1)
DD
IN
IN
value, based on design simulation and technology characteristics, not tested in
and temperature values.
6)
>V
ST7XXX
ST7XXX
DD
1)
5)
1)
2)
while a negative injection is induced by V
CMOS ports
V
V
Floating input mode
V
C
Between 10% and 90%
IN
DD
DD
SS
IN
L
=50pF
=
maximum must be respected, otherwise refer to I
≤
=5V
, f
V
V
SS
OSC
IN
Conditions
≤
V
, and T
DD
Figure 79. Typical I
V
DD
=5V
A
4)
unless otherwise specified.
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0
2
0.7xV
2 .5
Min
50
0
1
T a = 1 4 0 ° C
T a = 9 5 ° C
T a = 2 5 ° C
T a = -4 5 ° C
DD
3
PU
3 .5
IN
vs. V
PU
<V
Typ
V d d (V )
400
120
0.7
25
25
5
4
SS
current characteristics de-
DD
. Refer to
4 .5
with V
0.3xV
5
Max
± 25
250
± 4
INJ(PIN)
Figure
+4
±1
section 12.2.2
5 .5
DD
IN
=V
78). Static
specifica-
6
155/187
SS
Unit
t
mA
CPU
kΩ
µA
pF
ns
V