ST24 STMICROELECTRONICS [STMicroelectronics], ST24 Datasheet - Page 3

• Manufacturer Part Number: ST24
• Description: SERIAL 1K 128 x 8 EEPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 3. Device Select Code
Note: The MSB b7 is sent first.
Table 4. Operating Modes
Notes: 1. X = V
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: V
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
to act as a pull up (see Figure 3).
Bit
Device Select
Current Address Read
Random Address Read
Sequential Read
Byte Write
Multibyte Write
Page Write
2. Multibyte Write not available in ST24/25W01 versions.
Mode
IH
or V
(2)
IL
CC
b7
lock out write protect. In
1
CC
RW bit
(1)
’0’
’1’
’0’
drops down from the
’1’
’1’
’0’
’0’
b6
Device Code
0
MODE
V
V
X
X
X
X
IH
IL
b5
1
CC
CC
CC
1 to 128
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to V
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
mode, V
Write mode. When unconnected, the MODE input
is internally read as V
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W01 and
ST25W01 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
V
nected, the WC input is internally read as V
the memory area is not write protected.
b4
Bytes
0
IL
1
1
1
4
8
) the internal write protection. When uncon-
ST24/25C01, ST24C01R, ST24/25W01
IH
for Multibyte Write mode or V
b3
E2
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
CC
to act as pull up (see Figure 3).
Chip Enable
IH
E1
IL
b2
Initial Sequence
(Multibyte Write mode).
or V
IH
IH
for the Byte Write
) or disable (WC =
E0
b1
CC
IL
or V
for Page
RW
RW
b0
IL
SS
and
3/16
to