ml6696 Microsemi Corporation, ml6696 Datasheet

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ml6696

Manufacturer Part Number
ml6696
Description
100base-x Fiber Physical Layer
Manufacturer
Microsemi Corporation
Datasheet

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ml6696CH
Manufacturer:
MICROLINEAR
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20 000
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ml6696CQ
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ML
Quantity:
831
GENERAL DESCRIPTION
The ML6696 implements the complete physical layer of
the Fast Ethernet 100BASE-X standard for fiber media. The
device provides the MII (Media Independent Interface) for
interface to upper-layer silicon. The ML6696 integrates the
data quantizer and the LED driver, allowing the use of
low cost optical PMD components.
The ML6696 includes 4B/5B encoder/decoder, 125MHz
clock recovery/clock generation, LED driver, and a data
quantizer. The device also offers a power down mode
which results in total power consumption of less than 20mA.
The ML6696 is suitable for the current 100BASE-FX IEEE
803.2u standard defined using 1300nm optics, as well as
for the proposed 100BASE-SX standard defined using lower
cost 820nm optics
BLOCK DIAGRAM
CLKREF
TXCLK
TXER
TXEN
TXD3
TXD2
TXD1
TXD0
MDC
MDIO
COL
CRS
RXCLK
RXER
RXDV
RXD3
RXD2
RXD1
RXD0
CARRIER & COLLISION
4B/5B ENCODER
4B/5B DECODER
TRANSMIT
MACHINE
MACHINE
RECEIVE
LOGIC
STATE
STATE
AND
AND
PCS
PCS
DESERIALIZER
100BASE-X Fiber Physical Layer
INITIALIZATION
MANAGEMENT
SYNTHESIZER
NRZ TO NRZI
SERIALIZER
INTERFACE
INTERFACE
MII SERIAL
ENCODER
CLOCK
FEATURES
* Some Packages Are Obsolete
100BASE-FX physical layer with MII
Optimal 100BASE-SX solution (draft standard)
Integrated data quantizer (post-amplifier)
Integrated LED driver
125MHz clock generation and recovery
4B/5B encoding/decoding
Power-down mode
CLOCK & DATA
NRZI TO NRZ
RECOVERY
ENCODER
DRIVER
DATA QUANTIZER
(POST AMPLIFIER)
LED
CAPB
CAPDC
ML6696*
December 1998
LINK100
EDOUT
RTSET
IOUT
IOUT
EDIN
V IN+
ECLK
V IN–
1

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ml6696 Summary of contents

Page 1

... LED driver, and a data quantizer. The device also offers a power down mode which results in total power consumption of less than 20mA. The ML6696 is suitable for the current 100BASE-FX IEEE 803.2u standard defined using 1300nm optics, as well as for the proposed 100BASE-SX standard defined using lower ...

Page 2

... RXD0 16 RXCLK 17 CRS 18 COL 19 DGND3 TOP VIEW ML6696 64-Pin TQFP (H64-10 TOP VIEW 46 IOUT IOUT 45 44 AGND3 43 RTSET ...

Page 3

... TXCLK Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of this clock. 2 (10) RXD3 Receive data TTL output. Output is valid on RXCLK’s rising edge ...

Page 4

... TX PLL clock synthesizer and logic. This pin should be driven by an external 25MHz clock at TTL levels. Analog ground Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. ...

Page 5

... TXD2 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. 61 (5) TXD1 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD< ...

Page 6

... ML6696 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. V Supply Voltage Range ............................ –0. Input Voltage Range Digital Inputs ........................................... –0. VIN+, VIN-, CLKREF, CAPB, CAPDC ........ – ...

Page 7

... RTSET = 2.32k ±1% Current into All V Pins CC Current into All V Pins CC = Operating Temperature Range (Note 1) A CONDITIONS Note 2 Note 3 Note 3 Note 3 Note 4 25MHz Frequency Note 5 Note 5 Note 6, 7 Note 6, 7 ML6696 MIN TYP MAX UNITS 67.5 75 82.5 mA 0.1 mA 486 540 594 µA 200 295 ...

Page 8

... ML6696 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MII MANAGEMENT INTERFACE (MDC, MDIO) t Write Setup Time, MDIO Data Valid SPWS to MDC Rising Edge (1.4V Point) t Write Hold Time, MDIO Data Valid SPWH After MDC Rising Edge (1.4V Point) t Read Setup Time, MDIO Data Valid SPRS to MDC Rising Edge (1.4V Point) ...

Page 9

... TXCLKIN TXCLK TXD<3:0> TXER TXEN t TPS Figure 1. MII Transmit Timing RXCLK RXD<3:0> RXER RXDV t RCS Figure 2. MII Receive Timing MDC MDIO t SPWS Figure 3. MII Management Interface Write Timing t t TPWH TPWL t TPH t RPCR t RCH t SPWH ML6696 t RPCF 9 ...

Page 10

... PW1 t PW2 OP0 Figure 5. EEPROM Interface Timing t PW3 01 02 ECLK (INPUT TO ML6696) t PW4 t S1 EDOUT (INPUT TO ML6696 CPER t CPW t PER1 D14 D15 t DV1 16 BITS DATA ADDRESS t PER2 16 ...

Page 11

... ECLK to read out the 16 configuration bits. The EEPROM generates the configuration bit stream at EDOUT, synchronized with ECLK. Interface timing is shown in Figure important to note that the ML6696 expects LSBs first, whereas the 93LC46 shifts MSBs out first. Therefore, the data pattern must be reversed before programming it into the EEPROM ...

Page 12

... Not Used i.7 ISODIS Isolate bit disable (bit 0.10) i.6 REPEATER Repeater mode: when set to 1, CRS is only asserted when receiving non-idle signal at IN+/–, and ML6696 is forced to half duplex mode. i.5 - i.0 Not Used 12 FUNCTION OF RELATED PINS ECLK ECLK (Output clock to EEPROM) ECLK (Input clock from Microcontroller) No Effect Table 1 ...

Page 13

... Manual 1=100Mb/s Speed Select 0=10Mb/s 0.12 Not used 0.11 Power down 1=Power down 0=Normal operation 0.10 Isolate 1=Electrically isolate the ML6696 from MII 0=Normal operation 0.9 Not used 0.8 Duplex mode 1=Full duplex select 0=Half duplex select 0.7 Collision Test 1=Enable COL signal test 0=Normal operation 0.6 - 0.0 Not Used Table 3 ...

Page 14

... FX_TXLED 74HC04 470 C24 0.1µF 10µF AGND 850nm C24 0.1µF 10µF 1300nm AGNDQ Figure 7. ML6696 Typical Application Schematic 93LC46B 0.1µ DGND ...

Page 15

... SEATING PLANE Package: H64-10 64-Pin ( 1mm) TQFP 49 0.394 BSC 0.472 BSC (10.00 BSC) (12.00 BSC) 33 0.007 - 0.011 0.048 MAX (0.17 - 0.27) (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05) ML6696 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.600 BSC 0.690 - 0.730 (15.24 BSC) (17.53 - 18.54) 0.100 - 0.110 (2.54 - 2.79) 0º - 8º 0.003 - 0.008 (0.09 - 0.20) 0.018 - 0.030 (0 ...

Page 16

... ML6696 ORDERING INFORMATION PART NUMBER ML6696CH (Obsolete) ML6696CQ © Micro Linear 2000 registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; ...

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