sp5524 Zarlink Semiconductor, sp5524 Datasheet

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sp5524

Manufacturer Part Number
sp5524
Description
Bidirectional I2c Bus Controlled Synthesiser
Manufacturer
Zarlink Semiconductor
Datasheet

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sp5524 Summary of contents

Page 1

This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...

Page 2

... The SP5524 is a single-chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard BUS format. The device has six controllable open-collector output ports (P0-P3, P6 and P7), each capable of sinking 10mA. In addition 3-bit 5-level ADC input. The information 2 on these ports can be read via the I ...

Page 3

... SP5524 ELECTRICAL CHARACTERISTICS +4·5V to +5·5V. AMB CC These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Characteristic Supply current ...

Page 4

... DIV 48 PROGRAMMABLE COMP PRESCALER DIVIDER F 15 BIT DIVIDER CHARGE RATIO LATCH PUMP 6-BIT LATCH CONTROL PORT DATA INFORMATION LATCH Fig. 2 Block diagram SP5524 Units Conditions V V p-p V Port in off state V Port in on state With V applied ...

Page 5

... P7. The LSB of the address byte (R/W) sets the device into read mode high and write mode low. When the SP5524 receives a correct address byte it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are programmed ...

Page 6

... MA1 MA0 Voltage input 0· Always valid 1 0 0· 0·8V Table 4 Address selection SP5524 A Byte 1 A Byte 2 A Byte 3 A Byte 4 A Byte 5 A Byte 1 A Byte 0· 13· ...

Page 7

... IF SECTION 300 37· 12·5 100 50 6 130V 15V 22k 39n 180n 0·1 22k 2N3904 SP5524S 22k 12k 12k P2 12k P0 2N3906 IF SIGNAL Fig. 4 Typical application OPERATING WINDOW 500 1000 FREQUENCY (MHz) Fig. 5 Typical input sensitivity 112V 10k 47k ...

Page 8

... RF INPUTS 14 RF input V CC NOT ON P6 PORT Ports P0 - P3, P6 and P7 2 CRYSTAL Q1 3 CRYSTAL Q2 Reference oscillator Fig. 6 Input/output interface circuits CHARGE PUMP 170 16 DRIVE OUTPUT Loop amplifier 3k SCL/SDA * * ON SDA ONLY SCL and SDA inputs SP5524 V CC ACK 7 ...

Page 9

... SP5524 11: O NORMALISED 0 0 0.2 2 1·25GHz 0 Fig. 7 Typical input impedance FREQUENCY MARKER STEP = 250MHz ...

Page 10

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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