ST7263 STMICROELECTRONICS [STMicroelectronics], ST7263 Datasheet - Page 78

• Manufacturer Part Number: ST7263
• Description: LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263
I²C BUS INTERFACE (Cont’d)
5.7.5 Low Power Modes
5.7.6 Interrupts
Figure 41. Event Flags and Interrupt Generation
The I²C interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
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Mode
WAIT
HALT
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
*
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.
Description
No effect on I²C interface.
I²C interrupts exit from Wait mode.
I²C registers are frozen.
BERR
ARLO
ADSL
*
BTF
SB
AF
Interrupt Event
ITE
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
ADSEL
STOPF
Event
BERR
ARLO
Flag
BTF
SB
AF
Control
Enable
Bit
ITE
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
Exit
Halt
No
No
No
No
No
No
No