gm82c765b ETC-unknow, gm82c765b Datasheet - Page 20

• Manufacturer Part Number: gm82c765b
• Description: Floppy Disk Subsystem Controller
• Manufacturer: ETC-unknow

The Data Separator is a Digital Phase Lock
Loop Floppy Disk Data Separator (DPLL). It was
designed to address high performance error rates on
floppy
performance in terms of available bit jitter tolerance. It
contains the necessary logic to achieve classical 2nd
order, type 2, phase locked loop performance. DPLL is
used as the Data Separator in the GM82C765B system.
Figure 5 illustrates the DPLL implified block diagram.
The bit jitter tolerance for the data separator is 60%,
Which guarantees an error rate of < 10E-9.
The BM82C765B maintains the stand first level
algorithm to determine when write precompensation
should be applied.
The EARLY and LATE signals are used internally to
REFCLK
WRITE PRECOMPENSATION
DSKD
DATA SEPARATOR
disk
drives,
DETE-
CTION
H
A
P
S
E
and
Fig. 5. DPLL Simplified BLOCK DIAGRAM
SYNCHRONIZATION
to
DATA
provide
TRANSIENT RESPONSE
CLOCK GENERATION
STATE FILTERING
STEADY STATE
CD1
FREQUENCY
FILTERING
superior
CD2
20
select the appropriate delay in the write data pulse
stream.
the 16 MHz clock if this is the frequency on CLK1 pin
(23), and clocked through a shift register before a
multiplexer gates the chosen bit to the output.
i.e., one fourth of the bit cell period, and equal to one
half the WCLK period.
precompensated by + 187nS precompensation will be
generated. For frequencies other than 16 MHz on the
CLK1 pin, the precompensation values will be two and
three clock cycles respectively.
When the non-standard data rate using CLK2 is chosen,
the MFM precompensation will always be two clock
cycles.
For 9.6MHz, this is +208nS. In this case, this PCVAL
function is disabled
The output data pulse width has a 25% duty cycle,
The encoded WRITE DATA signal is synchronized to
When PCVAL pin (24) = 1, all data will be
SEPCLK
Phase
SCLK
CONTROLLED
OSCILLATOR
DIGITAL
RESYNCHRONIZATIO
SUMMER
RDATA
N
GM82C765B
SEPCLK
SEPD