cx20493-35/app Conexant Systems, Inc., cx20493-35/app Datasheet - Page 82
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cx20493-35/app
Manufacturer Part Number
cx20493-35/app
Description
With Cx20493 Smartdaa?
Manufacturer
Conexant Systems, Inc.
Datasheet
1.CX20493-35APP.pdf
(92 pages)
- Current page: 82 of 92
- Download datasheet (684Kb)
5.2.2
5-4
CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet
FCR - FIFO Control Register (Addr = 2, Write Only)
The FCR is a write-only register used to enable FIFO mode, clear the RX FIFO and TX
FIFO, enable DMA mode, and set the RX FIFO trigger level.
Bits 7-6
Bits 5-4
Bit 3
Bit 2
Bit 1
Bit 0
FCR7
FCR7 and FCR6 set the trigger level for the RX FIFO (Receiver Data Available)
When FIFO mode is selected (FCR0 = 1), FCR3 selects non-DMA operation (FCR3 =
RXRDY will be asserted when the number of characters in the RX FIFO is equal to or
TXRDY will be asserted when there are one or more empty (unfilled) locations in the
RXRDY will be asserted when there are one or more characters in the RX FIFO.
TXRDY will be asserted when there are no characters in the TX FIFO. TXRDY will go
When FCR2 is a 1, all bytes in the TX FIFO are cleared. This bit is cleared
When FCR1 is a 1, all bytes in the RX FIFO are cleared. This bit is cleared
When FCR0 is a 0, 16450 mode is selected and all bits are cleared in both FIFOs.
interrupt.
0) or DMA operation (FCR3 = 1). When FIFO mode is not selected (FCR0 = 0), this
bit is not used (the modem operates in non-DMA mode in 16450 operation).
greater than the value in the RX FIFO Trigger Level (IIR0-IIR3 = 4h) or the received
character timeout (IIR0-IIR3 = Ch) has occurred. RXRDY will go inactive when there
are no more characters in the RX FIFO.
TX FIFO. TXRDY will go inactive when the TX FIFO is completely full.
RXRDY will go inactive when there are no more characters in the RX FIFO.
inactive when the first character is loaded into the TX FIFO Buffer.
automatically by the modem.
automatically by the modem.
When FCR0 is a 1, FIFO mode (16550A mode) is selected and both FIFOs are
enabled. FCR0 must be a 1 when other bits in the FCR are written or they will not be
acted upon.
0
0
1
1
DMA operation in FIFO mode.
Non-DMA operation in FIFO mode.
RX FIFO Trigger Level.
Not used.
DMA Mode Select.
TX FIFO Reset.
RX FIFO Reset.
FIFO Enable.
FCR6
0
1
0
1
Conexant
RX FIFO Trigger Level (Bytes)
01
04
08
14
102247B
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