SC28L202A1 PHILIPS [NXP Semiconductors], SC28L202A1 Datasheet
SC28L202A1
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SC28L202A1 Summary of contents
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... SC28L202 Dual universal asynchronous receiver/transmitter (DUART) Objective specification Supersedes data of 2000 Jan 31 IC19 Data Handbook INTEGRATED CIRCUITS 2000 Feb 10 ...
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... EOS – Enhanced Operation Status Register UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) MR3 – Mode Register 3, A and ...
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... SOPR A and SOPR B – Set the Output Port Bits (OPR A and OPR B) ROPR A and ROPR B – Reset ROPR Output Port Bits (OPR A and OPR B) OPR – Output Port Register, A and for for B) THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS REGISTER DESCRIPTIONS Mode Registers MR1 Mode Register MR1 A[7] – ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) ISR – Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) LIST OF FIGURES Figure 1. Reset Timing (80XXX mode ...
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... SC26C92. Its differences from the SC26C92 are: 256–character receiver, 256 character transmit FIFOs, 3 and 5 volt compatibility, 8 I/O ports for each UART – 16 total, arbitrating interrupt system and overall faster buss and data speeds fabricated in an advanced 0.5 micron CMOS process that allows stand by current of less that 10 microamperes ...
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... Philips Semiconductors Dual UART ORDERING INFORMATION D Description i ti (Preliminary as of 1/31/00) (Preliminary as of 1/31/00) 52-Pin Plastic Quad Flat Pack (PQFP) 56-pin TSSOP 2000 Feb 10 Industrial V = +3.3 +5V 10 – +85 C amb SC28L202A1B SC28L202A1D 2 Objective specification SC28L202 D Drawing i Number Number SOT379-1 SOT364-1 ...
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... CPU the least significant bit. CEN I Chip Enable: Active–Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0–D7 as controlled by the WRN, RDN and A6–A0 inputs. When High, places the D0–D7 lines in the 3–State condition. ...
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... I Bus Configuration: When low configures the bus interface to the Conditions shown in this table. D0–D7 I/O Data Bus: Bi–directional 3–State data bus used to transfer commands, data and status between the DUART and the CPU the least significant bit. CSN I Chip Enable: Active–Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0– ...
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... Philips Semiconductors Dual UART 80xxx 56 Pin TSSOP Pin Function Pin Function 1 Vcc 29 CEN 2 Vss 30 WRN RDN TxDB I/O7B I/O6B 7 RxDA 35 I/O5B 8 RESET 36 I/O4B I/O3B I/O2B I/O1B I/O0B 13 Vcc 41 Vcc Vcc 15 Vss 43 Vss ...
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... Philips Semiconductors Dual UART 80xxx 52 Pin PQFP Pin Function Pin Function 1 RxDA 27 I/O5B 2 RESET 28 I/O4B I/O3B I/O2B I/O1B I/O0B 7 Vcc 33 Vcc 8 Vss 34 Vss I/O7A I/O6A I/O5A I/O4A I/O3A 14 RxDB 40 I/O2A 15 A2 ...
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... FIFO Structures The FIFO structure is 256 bytes for each of the four FIFOs in the DUART. They are organized as 11 bit words for the receiver and 8 bye words for the transmitter. The interrupt level may be set at any value from 0 to 255. The interrupt level is independently set for each FIFO ...
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... CEN, RDN, WRN pin combination. If the I/M pin is tied low the data is written to the device when the DACKN pin is asserted low by the DUART. Read data is presented by a delay from CEN active. The Host interface is comprised of the signal pins CEN, WRN RDN, (or R/WN) IACKN, DACKN, IRQN, 6 address pins and 8 three– ...
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... The two Counter/Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks or generating timeout periods. These clocks may be used by any or all of the receivers and transmitters in the DUART or may be directed to an I/O pin for miscellaneous use. Counter/Timer programming The counter timer is a 16–bit programmable divider that operates in one of four modes: character count, counter, timer, and time out ...
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... MR3 does not exist in 92 mode. MR3 is used in the control of the intelligent operations of the L202. Transmitter Status Bits The SR (Status Register, one per UART) contains two bits that show the condition of the transmitter FIFO. These bits are TxRDY and Tx Idle. TxRDY means the TxFIFO has space available for one or more bytes ...
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... Philips Semiconductors Dual UART followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits new character is not available in the TxFIFO, the TxD output remains High and the Tx Idle bit in the Status Register (SR) will be set to 1 ...
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... RxFIFO. The three status bits at the output of the RxFIFO are presented as the upper three bits of the status register included th has in each UART. The error status of a character, as reported by a read of the SR (status register upper three bits) can be provided in two ways ...
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... RxFIFO and MR0 [1:0] determines the sub mode as shown in the following list. MR3 [1: Normal Wake Up Mode (default) which is the same as previous DUARTs and is therefore controlled by the processor. The Host controls operation via interrupts it receives and commands it writes to the DUART command registers (CR). ...
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... Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR) resident in each UART. Programming of the IMR selects which of the above sources may enter the arbitration process. The IMR enables the interrupt. Only the bidders in the ISR whose associated bit in the IMR is set to one (1) will be permitted to enter the arbitration process ...
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... Philips Semiconductors Dual UART Address Recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the ICR (Interrupt Control Register). The transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt ” ...
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... Many users prefer polled to interrupt driven service where there are not a large number of fast data channels and/or the host CPU’s other interrupt overhead is low. The Dual UART is functional in this environment. The most efficient method of polling is the use of the ”update CIR” ...
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... Character and Address Recognition (Also used for Multi–drop, Xon/Xoff systems) Character recognition is specific to each of the two UARTs. Three programmable characters are provided for the character recognition for each channel. The three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to ” ...
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... The character recognition function and the associated interrupt generation is disabled on hardware or software reset. Multi–drop or Wake bit mode This mode is used to address a particular UART among a group connected to the same serial data source. Normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data ...
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... Dual UART PROGRAMMING THE HOST INTERFACE Writing control words into the appropriate registers programs the operation of the DUART. Operational feedback is provided via status registers that can be read by the CPU. The addressing of the registers is described in the Register Map. The contents of certain control registers are initialized to zero on RESET ...
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... IVR(7: IVR(7:1) + channel code 11 = IVR(7:5) + interrupt type + channel code DUART. If b’00, no vector will be presented during an IACKN cycle. The bus will be driven high (0xFF). If the field contains a b’01, the contents of the IVR, Interrupt Vector Register, will be presented as the interrupt vector without modification. ...
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... Bit 7 Bit 6 Reserved Reserved Set to 0 Set to 0 This register reports the enabled status of the several sub systems in the DUART. These systems are sometimes controlled by the state machines of the receiver FIFOs. EOS – Enhanced Operation Status Register Bit 7 Bit 6 Bit 5 Reserved ...
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... Philips Semiconductors Dual UART UART Registers These registers are generally concerned with formatting, transmitting and receiving data. The user must exercise caution when changing the mode of running receivers, transmitters, PBRG or counter/timers. The selected mode will be activated immediately upon selection, even if this occurs during the reception or transmission of a character ...
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... RTSN output signal, to control the CTSN (see MR2(4) description) input of the transmitting device not recommend to use the hardware flow control and the “in–band” (Xon/Xoff) flow control at the same time although the DUART hardware will allow it. To use the RTSN function: 1. Set MR1( ...
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... NOTE: 1. Add 0.5 to values shown for 0 – channel is programmed for 5 bits/char. MR2[7:6] – Mode Select The DUART can operate in one of four modes: Normal, Automatic Echo, Local Loop Back and Remote Loop Back MR2[7:6] = b’00 Normal Mode Normal and default mode The transmitter and receiver operating independently. MR2[7:6] = b’ ...
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... Philips Semiconductors Dual UART MR3 – Mode Register 3, A and B Bit 7 Bit 6 1 Xon/Xoff Address Recognition transparency transparency 0 = flow control characters 0 = Address characters received are loaded onto received are loaded to the RxFIFO RxFIFO 1 = flow control characters 1 = Address characters received are not loaded ...
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... Philips Semiconductors Dual UART RxCSR – Receiver Clock Select Register A and B TxCSR Transmitter Clock Select Register A and B Both registers consist of single 6–bit field that selects the clock source for the receiver and transmitter respectively. During a read the unused bits in this register read b’000. The “BRG” baud rates (fixed BRG rates) shown in the table below are based on the Sclk crystal frequency of 14 ...
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... Philips Semiconductors Dual UART CRx – Command Register Extension, A and used to write commands to the DUART. Bit 7 Bit 6 Lock Tx and Rx Enables Enable lock Rx & Tx state 0 = disable 1 = Change Rx & Tx state 1 = enable CR[7] – Lock Tx and Rx enables. If reset, the transmitter and receiver enable bits, CR[6:5] are not significant. The enabled/disabled state of a receiver or transmitter can be changed only if this bit is a “ ...
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... Philips Semiconductors Dual UART 10111 Host Xoff (or transmitter pause) command (CRTXoff). This command allows tight host CPU control of the flow control of the channel transmitter. When interrupted for receipt of a Xoff character by the receiver, the host may stop transmission of further characters by the channel transmitter by issuing the Host Xoff command ...
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... Philips Semiconductors Dual UART SR – Channel Status Register A and B Bit 7 Bit 6 Received Break Framing Error Yes 1 = Yes SR[7] – Received Break This bit indicates that an all zero character (including parity, if used) of the programmed length has been received with a stop bit at a logical zero. A single FIFO position is loaded with 0x00 when a break is received ...
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... This register provides the status of all potential interrupt sources for a UART channel. When generating an interrupt arbitration value, the contents of this register are masked by the interrupt mask register (IMR bit in the ISR is a ’1’ and the corresponding bit in the IMR is also a ‘ ...
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... Philips Semiconductors Dual UART IMR – Interrupt Mask Register A and B Bit 7 Bit 6 I/O Port Change of state Rx Watch–dog Time–out The programming of this register selects which bits in the ISR cause an interrupt output bit in the ISR is a ’1’ and the corresponding bit in the IMR is a ’ ...
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... Philips Semiconductors Dual UART TxFIL – Transmitter FIFO Interrupt Level A and B Bits 7:0 Any one of 256 FIFO empty positions The position in the Tx FIFO that caused the transmitter will enter the interrupt arbitration process. This register is used to offset the effect of the arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also “equalize” interrupt latency and allow for larger aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1. TxEL – ...
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... enable action action This register enables the UART’s Character Recognition, Address Recognition and Receiver watchdog timer. If both enable and disable are active a disable results. This register is used to enable the general–purpose character recognition feature WITHOUT 2000 Feb 10 ...
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... Philips Semiconductors Dual UART Programmable Counters, Timers and Baud Rate generators PBRGPU – Programmable BRG Timer Reload Registers, Upper 0 and 1 Bits 7:0 8 MSBs of the BRG Timer divisor. This is the upper byte of the 16–bit value used by the BRG timer in generating a baud rate clock PBRGPL – ...
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... Philips Semiconductors Dual UART CTPU Counter Timer Preset Upper 0 and 1 CTPU Bit 7 BIT 6 The lower eight (8) bits for the 16 bit counter timer preset register CTPL Counter –Timer Preset Low 0 and 1 CTPL Bit 7 BIT 6 The Upper eight (8) bits for the 16 bit counter timer preset register ...
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... Receive w errors 10 = Receive w/o errors The Current Interrupt Register is provided to speed up the specification of the interrupting condition in the DUART. The CIR is updated at the beginning of an interrupt acknowledge bus cycle or in response to an Update CIR command. (see immediately above) Although interrupt arbitration continues in the background, the current interrupt information remains frozen in the CIR until another IACKN cycle or Update CIR command occurs ...
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... Philips Semiconductors Dual UART Modification of the IVR Bits 7:3 Always contains bits (7:3) of the IVR The table above indicates how the IVR may be modified by the interrupting source. The modification of the IVR presented to the data bus during an IACK cycle is controlled by the setting of the bits (2:1) in the GCCR (Global Chip Configuration Register). ...
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... Philips Semiconductors Dual UART BCRx – Bidding Control Register – Xon/Xoff, A and B Bits 7:0 MSBs of an Xon/Xoff interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for a Xon/Xoff interrupt. BCRA – Bidding Control Register – Address, A and B Bits 7:0 MSBs of an address recognition event interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for an address recognition event interrupt. BCR C/T – ...
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... Philips Semiconductors Dual UART I/OPCR 0 – I/O Port Configuration Register Bits 7:6 Bits 5:4 I/O3 A control I/O2 A control 00 = GPI / TxC GPI / CT 0 Clock Input 01 = OPR[ OPR[ DTRN TxC A (16X) Output 10 = TxC A (1X) Output 11 = Reserved 11 = Reserved I/OPCR 1 – I/O Port Configuration Register Bits 7:6 Bits 5:4 I/O7 A control ...
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... Low 1=Pin Low This register is set by the SOPR and ROPR above. THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS The purpose of including previous functionality is to allow users to call communications code that may be used in former systems. When the registers in this lower 16–position address space is used it will revoke programming done in the upper address space where the addresses are duplicated ...
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... Philips Semiconductors Dual UART The following registers are unique for each Channel Mode Register MRn A MRn B Status Register Clock CSR A CSR B Select Command Register Receiver RxFIFO A RxFIFO B FIFO Transmitter TxFIFO A TxFIFO B FIFO Table 8. Baud Rate Generator Characteristics Crystal or Clock = 14 ...
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... Philips Semiconductors Dual UART REGISTER DESCRIPTIONS Mode Registers MR0 Mode Register 0 MR0 is accessed by setting the MR pointer to 0 via the command register command B. Bit 7 BIT 6 MR0 A Rx WATCH RxINT BIT 2 MR0 B DOG See Tables in MR0 B[3: Disable MR0 description are reserved 1 = Enable MR0[7] This bit controls the receiver watchdog timer disable enable ...
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... Philips Semiconductors Dual UART MR1 Mode Register 1 Bit 7 BIT 6 MR1 A Rx RxINT MR1 B CONTROLS BIT 1 RTS RxRDY 1 = Yes 1 = FFULL NOTE block error mode the block error conditions must be cleared by using the error reset command (command 0x40 receiver reset. MR1 A is accessed when the Channel A MR pointer points to MR1. ...
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... Philips Semiconductors Dual UART SR Status Register Bit 7 BIT RECEIVED FRAMING SR B BREAK* ERROR Yes 1 = Yes NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded when the corresponding data character is read from the FIFO. In block error mode, the error– ...
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... Philips Semiconductors Dual UART CSR A – Channel A Clock Select Register CSR A [7:4] – Channel A Receiver Clock Select This field selects the baud rate clock for the Channel A receiver. The field definition is shown in Table 13. CSR Clock Select Register Bit 7 BIT 6 CSR A & CSR B ...
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... Philips Semiconductors Dual UART CR Command Register Bit 7 BIT &CR B MISCELLANEOUS COMMANDS See Text of Channel Command Register NOTE: Access to the miscellaneous commands should be separated clock edges. A disabled transmitter cannot be loaded. COMMAND REGISTER TABLE A and B Commands 0xE, 0xF (marked with *) are global and exist only in channel A’s register space. ...
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... Philips Semiconductors Dual UART IPCR Input Port Configuration Register Bit 7 BIT 6 IPCR Delta Delta I change change 1 = change 1 = change IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change–of–State These bits are set when a change–of–state, as defined in the input port section of this data sheet, occurs at the respective input pins. ...
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... INTRN output. Note that the IMR does not mask the reading of the ISR – the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset. BIT 4 BIT 3 ...
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... Philips Semiconductors Dual UART CTVL Counter –Timer Value Lower (Counter/Timer 0) CTVL Bit 7 BIT 6 BIT 5 The lower eight (8) bits for the 16 bit counter timer value register Only the counter/timer 0 is available in the low order 16–position address map. Issuing the start command loads the C/T with the preset value ...
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... Philips Semiconductors Dual UART SOPR – Set Bits in the OPR Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits without keeping a copy of the OPR bit configuration. ...
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... Counter Timer Value Register Lower (CTVL 1) 2000 Feb 10 REGISTER MAP DETAIL (based on 28L92) Register Map NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a ”” symbol Addressing Scheme: ...
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... Philips Semiconductors Dual UART REGISTER MAP (BASED ON 28L92) NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a ” ” symbol A(6:0) READ EXTENSION 010 0000 (0x20) Mode Register 0 (MR0 A) NEW ADDRESS ...
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... Philips Semiconductors Dual UART REGISTER MAP (BASED ON 28L92) NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a ” ” symbol A(6:0) READ NEW 100 0000 (0x40) System Enable Status (SES A) ...
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... Philips Semiconductors Dual UART REGISTER MAP (BASED ON 28L92) NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a ” ” symbol A(6:0) READ GLOBAL 110 0000 (0x60) Interrupt Control Register (ICR) ...
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... Philips Semiconductors Dual UART 1 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER T Operating ambient temperature range amb T Storage temperature range stg 3 V Voltage from V to GND Voltage from any pin to GND SS P Power dissipation (PLCC44) P Power dissipation (PQFP44) Derating factor above 25 C (PLCC44) ...
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... Input port pins have active pull up transistors that will source a typical 2 A from Vcc when the input pins are at Vss. Input port pins at V source 0 All outputs are disconnected. Inputs are switching between CMOS levels See UART application note for power down currents less. 2000 Feb 10 123 ...
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... Philips Semiconductors Dual UART 1,2,3 AC CHARACTERISTICS (NOMINAL 5 VOLTS) Vcc = 5v 10 – +85 C unless otherwise specified Symbol Parameter Reset timing (See Figure 3) t Reset Pulse Width RES 5 Bus Timing (See Figure ___) t A6–A0 setup time to RDN, WRN Low *AS t A6–A0 hold time from RDN, WRN low ...
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... Philips Semiconductors Dual UART NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0 ...
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... Input port pins have active pull up transistors that will source a typical 2 A from Vcc when the input pins are at Vss. Input port pins at Vcc source 0 All outputs are disconnected. Inputs are switching between CMOS levels See UART application note for power down currents less. 2000 Feb 10 1,2,3 (NOMINAL 3 ...
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... Philips Semiconductors Dual UART 1,2,3 AC CHARACTERISTICS (NOMINAL 3.3 VOLTS) Vcc = 3.3v 10 – +85 C unless otherwise specified Symbol Parameter Reset timing (See Figure 3) t Reset Pulse Width RES Bus Timing (See Figure ___) t A6–A0 setup time to RDN, WRN Low *AS t A6–A0 hold time from RDN, WRN low ...
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... Philips Semiconductors Dual UART NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0 ...
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... Philips Semiconductors Dual UART X1/CLK A1–A4 RWN CSN D0– DTACKN NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. Figure 4. Bus Timing (Read Cycle) (68XXX mode) X1/CLK A1–A4 RWN CSN D0–D7 DTACKN NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. ...
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... Philips Semiconductors Dual UART X1/CLK INTRN IACKN D0–D7 DTACKN NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. RDN IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 2000 Feb 10 t CSC CSD t DAL t t DCR DAH Figure 6 ...
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... Figure 8. Interrupt Timing (80xxx mode) NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK t CLK t CTC t Rx *NOTE: X2 MUST BE LEFT OPEN SC28L92 X1 2pF 50k to 100k 4pF X2 14.7456MHz Figure 9. Clock Timing 64 Objective specification SC28L202 V +0. +0. SD00136 V CC 470 X1 X2* TO UART CIRCUIT SD00689 ...
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... Philips Semiconductors Dual UART TxC (INPUT) TxD TxC (1X OUTPUT) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) WRN CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 2000 Feb 10 1 BIT TIME ( CLOCKS) ...
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... Philips Semiconductors Dual UART D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP5) RDN STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR( and MR( MASTER STATION ADD#1 TxD TRANSMITTER ENABLED TxRDY (SR2) WRN MR1(4– ...
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... Philips Semiconductors Dual UART I = 2.4mA INTRN DACKN 125pF I = 2.4mA V return 400 A V return D0–D7 TxDA/B OP0–OP7 125pF Figure 15. Test Conditions on Outputs 2000 Feb 10 +5V for a 0 level CC for a 1 level SS SD00690 67 Objective specification SC28L202 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 2.0 mm 2000 Feb 10 68 Objective specification SC28L202 SOT379-1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 2000 Feb 10 69 Objective specification SC28L202 SOT364-1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) 2000 Feb 10 NOTES 70 Objective specification SC28L202 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. ...