ST72T331 STMICROELECTRONICS [STMicroelectronics], ST72T331 Datasheet - Page 38

• Manufacturer Part Number: ST72T331
• Description: 8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72E331 ST72T331
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T[5:0] bits contain the number of increments
Table 13.Watchdog Timing (f
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
5.3.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the device-specific Option Byte descrip-
tion.
5.3.5 Low Power Modes
5.3.6 Interrupts
None.
38/107
38
Mode
WAIT
HALT
diate reset
which represents the time delay before the
watchdog produces a reset.
Max
Min
Table
Description
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
1):
CR Register
initial value
C0h
FFh
WDG timeout period
CPU
= 8 MHz)
98.304
1.536
(ms)
5.3.7 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit .
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
STATUS REGISTER (SR)
Read /Write
Reset Value*: 0000 0000 (00h)
Bit 0 = WDOGF Watchdog flag .
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
* Only by software and power on/off reset
Note: This register is not used in versions without
LVD Reset.
WDGA
7
-
7
-
T6
-
T5
-
T4
-
T3
-
T2
-
T1
WDOGF
0
T0
0