alc658 Realtek Semiconductor Corporation, alc658 Datasheet - Page 22

• Manufacturer Part Number: alc658
• Description: Six-channel Ac?97 2.3 Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

6.1.17. MX2A Extended Audio Status and Control Register
Default: 05F0H
This register contains two active bits for power down and status of the surrounding DACs. Bits 1 & 2 are read/write bits which
are used to enable or disable DRA and S/PDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK slot
assignment of the S/PDIF. Bits 6, 7, & 8 are read-only bits that tell the controller when the Center, Surround, and LFE DACs
are ready to receive data. Bit 10 is a read-only bit that tells the controller if the S/PDIF configuration is valid. Bits 11, 12, and
13 are read/write bits which are used to power down the Center, Surround, and LFE DACs respectively.
Note 1: SPCV is a read-only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the
configuration is supported, SPCV is set as 1 by H/W. The driver can check this bit to determine the status of the S/PDIF
transmitter system. SPCV is always operating, independent of the S/PDIF enable bit (MX2A.2). The S/PDIF output is active if
MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid (SPCV=0), channel status is still output,
but the output data bits will be all zero. The condition to allow S/PDIF output is S/PDIF(MX2A.2)=1 & SPACV=1,
otherwise S/PDIF output will be all zeros when MX2A.2=1 and SPACV=0 (invalid).
Note 2: Only front DACs support a 96KHz sample rate when DRA=1. MX2A.1 only selects a clock source for the front DACs.
Software must mute surround DACs and CEN/LFE DACs.
Six-Channel AC’97 2.3 Audio Codec
5:4
Bit
15
14
13
12
11
10
9
8
7
6
3
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
-
-
-
Function
VCFG. Validity Configuration of S/PDIF Output
Combined with MX3A.15 to decide validity control in S/PDIF output signal.
Reserved.
Power Down LFE DAC. (PRK)
0: Normal
1: Power down LFE DAC
Power Down Surround DAC. (PRJ)
0: Normal
1: Power down Surround DAC
Power Down Center DAC. (PRI)
0: Normal
1: Power down Center DAC
SPCV (S/PDIF Configuration Valid)
0: Current S/PDIF configuration {SPSA, SPSR, DAC/slot rate} is not valid
1: Current S/PDIF configuration {SPSA, SPSR, DAC/slot rate} is valid
Reserved
LFE DAC Status (LDAC).
Surround DAC Status (SDAC). 0: Not yet
Center DAC Status (CDAC).
SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=0
00: S/PDIF-Out source is from AC-LINK slot3/4.
01: S/PDIF-Out source is from AC-LINK slot7/8.
10: S/PDIF-Out source is from AC-LINK slot6/9.
11: S/PDIF-Out source is from AC-LINK slot10/11. (Default)
SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=1(for 96K S/PDIF-Out)
01: S/PDIF-Out source is from AC-LINK slot3/4 + slot7/8.
Reserved
S/PDIF Enable. 1: Enable 0: Disable (Hi-Z)
DRA Enable. 1: Enable 0: Disable ‡
VRA Enable. 1: Enable 0: Disable
Table 23. MX2A Extended Audio Status and Control Register
0: Not yet
0: Not yet
18
1: Ready
1: Ready
1: Ready
Datasheet
ALC658
Rev. 1.3