32C87 RENESAS [Renesas Technology Corp], 32C87 Datasheet - Page 82

• Manufacturer Part Number: 32C87
• Description: RENESAS MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 82 of 85
Figure 5.9
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
WR,WRL,WRH
Read Timing (1 φ + 1 φ Bus Cycle)
Write Timing (1 φ + 1 φ Bus Cycle)
BCLK
BCLK
BHE
BHE
ADi
ADi
CSi
RD
CSi
DBi
DBi
NOTES:
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
2. Varies with operation frequency:
3. Varies with operation frequency:
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
td(DB-WR) = (tcyc x m - 20) ns.min
th(WR-DB) = (tcyc / 2 - 20) ns.min
th(WR-AD) = (tcyc / 2 - 15) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
td(BCLK-AD)
td(BCLK-AD)
VCC1 = VCC2 = 3.3 V Timing Diagram (3/4)
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + b φ , m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a φ + b φ , n = a + b)
(if external bus cycle a φ + b φ , n = (b x 2) - 1)
18ns.max
td(BCLK-RD)
td(BCLK-CS)
18ns.max
td(BCLK-CS)
18ns.max
18ns.max
( if external bus cycle a φ + b φ , m = b)
tcyc
tcyc
(1)
(1)
Hi-Z
td(BCLK-WR)
18ns.max
18ns.max
tac1(AD-DB)
tac1(RD-DB)
td(DB-WR)
(2)
tsu(DB-BCLK)
30ns.min
tw(WR)
(3)
(2)
(1)
(3)
th(WR-DB)
th(WR-AD)
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
th(WR-CS)
th(BCLK-WR)
0ns.min
tcyc=
(3)
(3)
(3)
th(BCLK-CS)
-3ns.min
th(BCLK-AD)
-3ns.min
th(BCLK-RD)
-5ns.min
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
f(BCLK)
th(RD-CS)
0ns.min
th(RD-AD)
0ns.min
th(RD-DB)
0ns.min
10
9
VCC1=VCC2=3.3V
5. Electrical Characteristics