hd66765 Renesas Electronics Corporation., hd66765 Datasheet - Page 37

• Manufacturer Part Number: hd66765
• Description: 396-channel Segment Driver With Internal Ram For 4096-color Displays - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

Serial Data Transfer
Setting the IM1 pin to the GND level and the IM2 pin to the Vcc level allows standard clock-
synchronized serial data (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL),
serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses
an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at
Vcc or GND.
The HD66765 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It
ends serial data transfer at the rising edge of CS* input.
The HD66765 is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66765. The HD66765, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be
assigned to a single HD66765 because the seventh bit of the start byte is used as a register select bit (RS):
that is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an
instruction can be issued or data can be written to or read from RAM. Read or write is selected according
to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted
when the R/W bit is 1.
After receiving the start byte, the HD66765 receives or transmits the subsequent data byte-by-byte. The
data is transferred with the MSB first. All HD66765 instructions are 16 bits. Two bytes are received with
the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been
received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is
fetched internally as the lower eight bits of the instruction.
Four bytes of RAM read data after the start byte are invalid. The HD66765 starts to read correct RAM
data from the fifth byte.
Table 18
Transfer Bit
Start byte format
Note: ID bit is selected by the IM0/ID pin.
Table 19
RS
0
0
1
1
R/W
0
1
0
1
Start Byte Format
RS and R/W Bit Function
Function
Sets index register
Reads status
Writes instruction or RAM data
Reads instruction or RAM data
S
Transfer start
1
Device ID code
0
37
2
1
3
1
4
1
5
0
6
ID
HD66765
7
RS
8
R/W