hd66420 Renesas Electronics Corporation., hd66420 Datasheet
hd66420
Related parts for hd66420
hd66420 Summary of contents
Page 1
... LCD panel with four-level grey scale. A single HD66420 can display a maximum of 160x80 dots using its powerful display control functions. It can display only eight lines out of eighty lines. This function realize low power consumption because high voltage for driving LCD is not needed ...
Page 2
... HD66420 Wide range of instructions reversible display, display on/off, vertical display scroll, blink, reversible address, read-modify-write mode Package: TCP Ordering Information Type No. HD66420TA0 2 Package TCP ...
Page 3
... RES VCC4 GND4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCC5 GND5 VCC6 VLCD4 GND6 Note: This figure is not drawn to a scale HD66420 COM80 COM79 COM78 COM41 SEG160 SEG159 SEG158 SEG3 SEG2 SEG1 COM40 COM39 COM3 COM2 COM1 3 ...
Page 4
... V : +2.2V to +5.5V, GND Power supply to LCD driving circuit Several levels of power to the LCD driving outputs. Master HD66420 outputs these levels to the slave HD66420. Must be connected to external resister when using R-C oscillation. When using an external clock, it must be input to the OSC terminal. Clock output ...
Page 5
... GP44 GP43 GP42 GP41 GP40 W CM1 CM0 CC4 CC3 CC2 – – – – – – – – – – – – – – – HD66420 1 0 IR1 IR0 HOLT ADC BLK XA1 XA0 YA1 YA0 D1 D0 ST1 ST0 BK6 BK7 BK9 PB1 ...
Page 6
... HD66420 RMW RMW = 1: Read-modify-write mode; Address is incremented only after write access RMW = 0: Address is incremented after both write and read access DISP DISP = 1: Display on DISP = 0: Display off STBY STBY = 1:Internal operation and power circuit halt; display off STBY = 0: Normal operation PWR PWR = 1: Output ‘High’ from DCON PWR = 0: Output ‘ ...
Page 7
... DTY1 (1,1): 1/8 display duty cycle - Partial display DTY1 (1,0): 1/32 display duty cycle DTY1 (0,1): 1/64 display duty cycle DTY1 (0,0): 1/80 display duty cycle INC INC = 1: X address is incremented for each access INC = 0: Y address is incremented for each access BLK BLK = 1: Blink function is used BLK = 0: Blink function is not used HD66420 7 ...
Page 8
... HD66420 Block Diagram COM1 COM40 SEG1 Row Driver Column Driver Level Shifter Level Shifter Attribute Grey scale selector Data Latch2 Data Latch1 320 x 80bit Display memory X Decoder Data Buffer X Address Counter Y Address Counter Blink Registers Start Line Register Blink Start Line Register ...
Page 9
... LCD panel. Four levels of gray scale can be selected from 32-levels, so the appropriate 4-level gray scale can be displayed. The HD66420 can reduce power dissipation without affecting display because data is retained in the display RAM even during standby modes. An LCD system can be configured simply by attaching external power supply, capacitors and resistors (figure 1) since the HD66420 incorporates power circuits ...
Page 10
... HD66420 MPU Interface The HD66420 can interface directly to an MPU through an 8-bit data bus or through an I/O port (figure 2). The MPU can access the HD66420 internal registers independently of internal clock timing. The index register can be directly accessed but the other registers (data registers) cannot. Before accessing a data register, its register number must be written to the index register ...
Page 11
... DB7 to Data Data DB0 Write index Write data register register Figure 3 8-Bit Data Transfer Sequence Data Data Write data Write index Read data register register register HD66420 Data Data Read data register 11 ...
Page 12
... HD66420 LCD Driver Configuration Row and column outputs: The HD66420 outputs row signals from both sides. In any case, each output’s function is fixed; COM1 to COM80 output row signals and SEG1 to SEG160 output column signals. Row outputs from both sides of LCD 40-channel ...
Page 13
... H’0 on the top left of an LCD panel regardless of where it is positioned with respect to the panel. This is because the HD66420 can invert the positional relationship between display RAM addresses and LCD driver output pins by inverting RAM addresses. Specifically, the HD66420 outputs data in address H’ ...
Page 14
... The power supply circuit of slave LSI stop working levels are supplied from the master LSI. If the internal power supply circuit can not drive two LSIs, use an external power supply circuit. Figure 6 shows the configuration using two HD66420s and table 2 lists the differences between master and slave modes. ...
Page 15
... Registers R0 R15 R1: BIS1, 0 R1: other R16 Power supply circuit Master Mode Slave Mode Must be set high Must be set low Oscillation is active Oscillation is active Output High-Z Output signals Input signals Valid Valid Valid Invalid Valid Valid Valid Invalid Valid Invalid HD66420 15 ...
Page 16
... HD66420 Display RAM Configuration and Display The HD66420 incorporates a bit-mapped display RAM. It has 320 bits in the X direction and 80 bits in the Y direction. The 320 bits are divided into forty 8-bit groups. As shown in figure 6, data written by the MPU is stored horizontally with the MSB at the far left and the LSB at the far right. The consecutive two bits control one pixel of LCD, this means that one 8-bits data contains data which controls four pixels ...
Page 17
... LCD drive signal output SEG1 H’00 H’01 H’4E H’4F H’0 H’1 X addresses MSB (a) ADC = 0 Figure 8 Display RAM Configuration LCD drive signal output SEG1 SEG160 H’00 H’01 H’4E H’4F H’26 H’27 H’27 X addresses MSB (b) ADC = 1 HD66420 SEG160 H’0 17 ...
Page 18
... HD66420 Word Length The HD66420 can handle either 8- or 6-bits as a word. In the display memory, one X address is assigned to each word 6-bits long in X direction. When the 6-bits mode is selected, only data on DB5 to DB0 are used and data on DB7 and DB6 are discarded ...
Page 19
... Figure 10 Display RAM Bits Map H’ (a) WLS= 1, ADC = H’35’s bit7,6, and are disable . H’ (b) WLS= 1, ADC = H’0’s bit7 to 2 are disable HD66420 19 ...
Page 20
... Packed Pixel Method For grey scale display and super reflective colour display, multiple bits are needed for one pixel. In the HD66420, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour display. One address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as consecutive bits in one byte ...
Page 21
... The HD66420 uses PWM, Pulse Width Modulation, technique for gray scale display. A period of one line is divided into thirty-one or four and HD66420 outputs turn-on levels for one period and turn-off levels for rest of these period. This technique changes gray scale on monochrome display and colour on super reflective colour panel ...
Page 22
... HD66420 Table 4 Value of a Palette Register and Grayscale Levels (GRAY= 0) Value ...
Page 23
... Access to Display RAM by the MPU: To access the display RAM, first write the RAM address desired to the X address register (R2) and the Y address register (R3). Then read/write the display memory access register (R4). Memory access by the MPU is independent of memory read by the HD66420 and is also asynchronous with the HD66420’s clock, thus enabling an interface independent of HD66420’s internal operations. However, when reading. data is temporarily latched into a H66420’ ...
Page 24
... HD66420 Address Input H’02 [n] data Output data Address [*,*] Figure 12 Display RAM read sequence 24 Y Address H’03 H’04 [m] Undetermined [n,*] [n,m] Dummy read Data[n,m] Data[n,m+1] [n,m+1] [n,m+2] ...
Page 25
... Data is read by the HD66420 to be displayed asynchronously with accesses by the MPU. However, because simultaneous access could damage data in the display RAM, the HD66420 internally arbitrates access timing; access by the MPU usually has priority and so access by the HD66420 is placed between accesses by the MPU. Accordingly, an appropriate time must be secured (see the given electrical characteristics between two accesses by the MPU). H’ ...
Page 26
... RAM at read-modify-write mode. The data which is read from the display RAM may be modified and written to the same address without re-setting the address. Data is temporarily latched into a HD66420’s buffer and then output next time a read is performed in a subsequent cycle. This means that the dummy read is necessary after every cycle ...
Page 27
... Vertical Scroll Function The HD66420 can vertically scroll a display by varying the top raster to be displayed. which is specified by the display start raster register. Figure 15 and 16 show vertical scroll examples. As shown, when the top raster to be displayed is set to l, data in Y address H’00_ is displayed on the 80th raster. To display another frame on the 80th raster, therefore, data in Y address H’ ...
Page 28
... HD66420 Y-address Top raster to be displayed = 0 Y-address Top raster to be displayed = 1 Y-address Top raster to be displayed = 2 Figure 15 Vertical Scroll : 1/80Duty Cycle 28 H’00 H’01 H’02 H’03 H’04 H’05 H’06 H’07 H’08 H’09 H’0A H’4C H’4D H’4E H’4F H’01 H’02 H’03 H’04 H’ ...
Page 29
... Top raster to be H’05 displayed = 1 H’06 H’07 H’08 H’09 H’0A H’0B H’3D H’3E H’3F H’40 Y-address H’02 H’03 H’04 H’05 H’06 H’07 H’08 Top raster to be H’09 displayed = 2 H’0A H’0B H’0C H’3E H’3F H’40 H’41 Figure 16 Vertical Scroll : 1/64Duty Cycle HD66420 29 ...
Page 30
... HD66420 Partial Display Function The HD66420 can display only a part of a full display. The bias ratio of this partial display is 1/4 from V to GND, the duty ratio is 1/8 and rest of display is scanned with unselected levels. 8 levels of contrast can be selected wit data bit R16. The position of this partial display can be located at any position with using partial display position register ...
Page 31
... Y address H’00 Display RAM Start line R5 ABCD R5+7 H’4F Figure 17 Partial Display LCD panel ABCD R11 = H’04 HD66420 COM1 COM33 COM40 COM80 COM41 31 ...
Page 32
... HD66420 Blink Function The HD66420 can blink a specified area on the dot-matrix display. Blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. For example, when the frame frequency is 80 Hz. the area is turned on and off every 0.8 seconds. ...
Page 33
... Display start raster = 0 Blink start raster = 0 Blink end raster = H’F Figure 19 Scrolling Blink Area HD66420 Display start raster = H’5 Blink start raster = H’5 Blink end raster = H’F 33 ...
Page 34
... RAM and internal registers except the DISP bit are retained. However, only control registers can be accessed during standby mode. HD66420 has an another power down mode: partial display. In this mode only a part of display is active. However, this duty ratio is 1/8 so the external power supply for LCD drive will be inactive ...
Page 35
... Set HOLT bit to 1 (control register 1) Set DTY or GRAY bit to 1 (control register 2) Wait for oscillation to stabilize Clear HOLT bit to 0 (control register 1) Figure 21 Procedure for Changing Oscillator HD66420 Internal operation stops Oscillator 2 starts working Internal operation starts 35 ...
Page 36
... HD66420 Power On/Off Procedure Figure 22 shows the procedure for turning the power supply on and off. This procedure must be strictly followed to prevent incorrect display because the HD66420 incorporates a power supply circuit. Turn on power (power-on reset) Set PWR bit to 1 (control register 1) Set CNF, ADC, DTY1, DTY0, INC bits according to ...
Page 37
... Oscillator The HD66420 incorporates two sets of R-C oscillator for two display modes: OSC-OSC1 oscillator is used for 32-levels gray scale display mode and OSC-OSC2 oscillator for 4-levels gray scale display mode. If the internal oscillator is not used, an appropriate clock signal must be externally input through the OSC pin. In this case, the OSC1 and OSC2 pins must be left unconnected ...
Page 38
... LCD Drive Voltage Power Supply Levels: To drive the LCD, a 6-level power supply is necessary. These levels are generated internally or supplied from outside. When an internal voltage levels generator is chosen, external capacitors are needed to stabilize these levels. AS the HD66420 incorporates operational amplifiers to these levels, this circuit gives better quality of display with less power consumption. This divided ratio is programmable ...
Page 39
... LCD drive levels bias ratio: LCD driving levels bias ratio can be selected from 1/6, 1/7, 1/8 or 1/9. Power Supply: The HD66420 needs the external power supply for LCD driving circuit. If this power circuit has on/off control, the HD66420 controls the external power supply circuit by setting PWR bit. ...
Page 40
... HD66420 VLCD Vcc IREFP r IV1 GND R4 r IV2 IREFM Resister for bias current IV3 of operational amplifier r IV4 r IV5 resistive divider for partial display mode HD66420 Figure 24 Power Supply Circuit 40 VLCD Operational amplifier OFF V1O V2O Bias R3 control - C1 + V3O ...
Page 41
... Reset The low RES signal initializes the HD66420, clearing all the bits in the internal registers. During reset. the internal registers cannot be accessed. Note that if the reset conditions specified in the Electric Characteristics section are not satisfied, the HD66420 will not be correctly initialized. In this case, the internal registers of the HD66420 must be initialized by software ...
Page 42
... HD66420 Control Register 1 (R0): Control register 1 (figure 26) controls general operations of the HD66420. Each bit has its own function as described below. RMW bit RMW = l: Read-modify-write mode Address is incremented only after write access RMW = 0: Address is incremented after both write and read accesses DISP bit ...
Page 43
... RMW DISP STBY PWR Set value Figure 26 Control Register 1 (R0) Control Register 2 (R1): Control register 2 (figure 27) controls general operations of the HD66420. Each bit has its own function as described below. BIS1, BIS0 bits BIS1 (1, 1): 1/6 LCD drive levels bias ratio BIS1 (1, 0): 1/7 LCD drive levels bias ratio ...
Page 44
... HD66420 Y Address Register (R3): The Y address register (figure 29) designates the Y address of the display RAM to be accessed by the MPU. The set value must range from H’00 to H’40; setting a greater value is ignored. The set address is automatically incremented each time the display RAM is accessed not necessary to update the address each time. Data bit 7 is unused ...
Page 45
... Data bits are unused; they should be set to 0 when written to ST6 ST5 ST4 ST3 ST2 BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 HD66420 ST1 ST0 1 0 BSL0 1 0 BEL0 45 ...
Page 46
... HD66420 Data bit 7 R8 Set value BK0 Set value R9 BK8 R10 Set value Figure 34 Blink Registers (R8, R9, R10) Data bit 7 6 Set value Set value Row no. H’00 COM1 to COM8 H’01 COM9 to COM16 H’02 COM17 to COM24 H’03 COM25 to COM32 H’04 COM33 to COM40 ...
Page 47
... Level GP44 GP43 GP42 1/31 2/31 3/31 4/31 1 5/31 6/31 7/31 8/ 9/31 10/31 11/31 12/31 1 13/31 14/31 15/31 Alternative Cycle Frame 7 lines 11 lines 13 lines CM1 CM0 CC4 CC3 CC2 HD66420 GP11 GP10 GP21 GP20 Gray GP31 GP30 scale GP41 GP40 Level 0 0 16/31 1 17/ 18/31 1 19/ 20/31 1 21/ 22/31 1 23/ 24/31 1 25/ 26/31 1 ...
Page 48
... HD66420 Absolute Maximum Ratings Item Power Supply Logic circuit voltage LCD drive circuit Input voltage 1 Input voltage 2 Operation temperature Storage temperature Notes: 1. Measured relative to GND 2. Applies to pins M/S, OSC, OSC1, OSC2, DB7 to DB0, RD, WR, CS, RS, RES, CL1, M, FLM 3. Applies to pins V1O, V2O, V3O, V4O and V5O 4 ...
Page 49
... VLCD = 6 V 0.8 V — — 0 — — 0 — — — — HD66420 *10 Notes to GND 100 – =3 ...
Page 50
... HD66420 4-levels gray scale mode; GRAY = 3.0V CC Checker board is displayed No access fro CPU 8. Measured during stand-by mode 3. Specified under following conditions: Internal power supply circuit is used. Resister value is 5M which is connected between IREFM and GND V = 3.0V, VLCD = 12V, IREFP = V CC 10. Specified at +75 C for die products. ...
Page 51
... HD66420 * Notes Rf = 240 3 Notes Notes ...
Page 52
... HD66420 t WRDL RS,CS t DDR DB7- DB0 52 t WRDH t t WWRH DHR Figure 39 MPU Interface WWRL DSW t DHW ...