SI3452 SILABS [Silicon Laboratories], SI3452 Datasheet - Page 2
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SI3452
Manufacturer Part Number
SI3452
Description
QUAD HIGH-VOLTAGE PORT CONTROLLER FOR POE AND POE+ PSES
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.SI3452.pdf
(36 pages)
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Si3452/3
Description
When connected directly to the host system or configured in Auto mode, each Si3452/3 high-voltage port controller
provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage
interfaces of four complete PSE ports. The Si3452/3 fully integrates robust, low-R
MOSFET switches, low-power dissipation current sensing circuitry, and transient voltage surge suppression
devices.
The on-chip current sense circuitry and power MOSFETs provide programmable scaling of current limits to match
either PoE (350 mA, 15.4 W), PoE+ (600 mA, 30 W), and extended (800 mA, 40 W) power requirements on a per-
port basis. Designed for use in Endpoint PSE (e.g., Ethernet switches) or Midspan PSE (e.g., inline power
injectors) applications, each Si3452/3 also performs the IEEE-required powered device (PD) detection,
classification, and disconnect functionality.
The flexible architecture enables powered device disconnect detection using either dc disconnect (Si3453) or
Silicon Laboratories' proprietary dV/dt disconnect (Si3452) sensing algorithm. dV/dt disconnect is an alternative to
dc disconnect that requires no additional BOM components, does not dissipate extra device power, and fully
interoperates with all powered devices. Also provided are multi-point detection algorithms and per-port current and
voltage monitoring.
Intelligent protection circuitry includes power supply under-voltage lockout (UVLO), port output current limiting and
short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge-suppressors
capable of protecting the Si3452/3 from a variety of harsh surge events seen on the RJ-45 interface.
To maximize system design flexibility and minimize cost, each Si3452/3 connects directly to a system host
controller through an I
of 12 unique addresses, allowing control of up to 48 ports on a single I
Functional Block Diagram
2
8 kByte EPROM
WDT
256 Byte SRAM
POR
& PSE FSM
MCU Core
I2C
10b
ADC
2
C serial interface, eliminating the need for an external MCU. The Si3452/3 can be set to one
PLL
Regulator
& Monitor
Voltage
LV SPI
Sensor
Temp
VREF & Central Bias
PGA
Control
HV SPI
Port
&
Rev. 1.0
Channel
Thermal
Control
Mode
Limit
Prot.
&
2
C bus.
PER PORT ANALOG
Gate Control,
Current Limit
Classification
Current
Disconnect
& Foldback
Sense
Detection
DC or
dV/dt
&
ON
(0.3 typical) power
DET4
DET3
DET2
VOUT4
VOUT3
VOUT2
VOUT1
DET1