V4082V1ST3B EMMICRO [EM Microelectronic - MARIN SA], V4082V1ST3B Datasheet - Page 5

• Manufacturer Part Number: V4082V1ST3B
• Description: Identification ROM
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

Functional Description
The V4082 is a 64-bit read only memory (ROM) which
contains a unique laser engraved serial number, the data
in the ROM is partitioned into three sections: an 8-bit
type identifier code, a 48-bit serial number and an 8-bit
cyclical redundancy check (CRC). A signal interface lead
provides communication for reading and writing. Power
for reading is derived from the data line itself with no
need for an external power source.
available in SOT 223 or TO-92 package.
Operation
All communication to and from the V4082 Silicon Serial
Number is accomplished via a single interface lead.
Data contained within the V4082 is accessed through the
use of time slots and a single wire protocol. Power to the
part is derived from the high going pulse at the beginning
of a write or read time slot.
Write time slots
A write time slot is initiated when the system pulls the
data line from a high logic level to a low logic level.
There are two types of write time slots: write one and
write zero.
microseconds and a maximum of 120 microseconds in
duration with a minimum of a 1 microsecond syncpulse
between individual write cycles.
For the system to generate a write one time slot, the data
line must be pulled to a logic low level and then released,
allowing the data line to pull up to a high level within 15
microseconds after the start of the write time slot (see
Figure 4a).
For the system to generate a write zero time slot, the
data line must be pulled to a logic low level and remain
low for the duration of the write time slot (see Figure 4b).
Read time slots
The system generates read time slots when data is to be
read from the V4082. A read time slot is initiated when
the system pulls the data line from a logic high level to a
logic low level. The data line must remain at a low logic
level for a minimum of 1 microsecond and a maximum of
15
microseconds includes the time required for the data line
to pull up to a high level after it is released. The state of
the V4082 data must be read by the system within 15
microseconds after the start of the read time slot. After
this time, the state of the data is not guaranteed (see
Figure 5). All read time slots must be a minimum of 1
microsecond syncpulse between individual read time
slots.
Single wire protocol
To communicate with the V4082 a specific protocol is
utilized.
separate states which are used to reset the device, issue
a command word, read the type identifier number and
read the unique silicon serial number and CRC byte (see
Figure 4).
To initially set the V4082 into a known state, a reset
pulse must be sent to it. The reset pulse is a logic low
generated by the system which must remain low for a
minimum of 480 microseconds and then be followed by a
480 microsecond logic high level (see Figure 3). During
these 480 microsecond high time the V4082 will assert a
presence detect signal. This signal is generated by the
Copyright © 2004, EM Microelectronic-Marin SA
microseconds.
The single wire protocol consists of four
All write slots must be a minimum of 60
This
maximum
The circuit is
time
of
15
5
V4082 and consists of a logic low level which is held for
a maximum of 240 microseconds and minimum of 60
microseconds. This signal can be used to detect that a
V4082 is attached to the single wire interface after the
issuance of a reset command.
Once the V4082 has been set into a known state, the
command word is transmitted to the V4082 with eight
write time slots. LSB first. The command word for the
V4082 is a hexadecimal 0Fh.
Upon recognition of the command word, the V4082 is
ready to respond with its data. The data in the ROM is
partitioned into three sections: an 8-bit identifier code, a
48-bit serial number and an 8-bit CRC.
identifier code for the V4082 is 81h. The 48-bit serial
number in each V4082 is unique. The single wire CRC
algorithm calculates an 8-bit CRC, from the type identifier
code and the serial number (56 bits) and generates an 8-
bit value. This value is lasered into the part at the time of
manufacture. To terminate a read operation: either give
64 read time slots or issue a reset sequence.
CRC generation
To validate that the transmitted data from the V4082 has
been received correctly by the system, a comparison of
the system-generated CRC and the received V4082
CRC must be made. If the two CRC values match, the
transmission was error-free.
The equivalent polynomial function of the CRC is: CRC
= x
Recommended system interface
The system must have an open drain driver with a pull up
resistor of approximately 5KΩ to VCC on the data signal
line. The V4082 has an internal open drain driver with a
1.2MΩ pulldown resistor to ground.
resistor holds the data input pin at ground potential when
the V4082 is not connected to a single wire interface. To
avoid unnecessary current consumption, VCC may either
be disconnected or pulled to ground when the V4082 is
not used.
Effect of Cext
Any capacitance on the data pin forms a time constant
together with the external pull-up resistor RPUP or the
pull-down resistances of either the external open-drain
driver or the modulator FET of the V4082. The pull-up
time constant TPUP = RPUP*Cext is normally the most
critical one.
given in Table 4 are with respect to the Data Input Logic
Thresholds VIL and VIH. In the case of read operation,
the VIH of the external master circuit (RX input) has to be
taken into account. Cext has to be kept sufficiently low
to allow the pulling-up of the DATA pin to VIH of the
master circuit before the Read Data Valid Time (TRDV)
in case of a Read 1. For the very first pulling-up of the
data pin, i.e. after a reset pulse, the on-chip supply buffer
capacitance (approx. 500 pF) has to be considered as
well. Later on this capacitance has less influence on the
operation, the on-chip supply is well above the VIH level
and the on-chip capacitor is decoupled by the diode from
the data pin for VDATA voltages lower than the on-chip
supply.
8
+ x
5
+ x
4
+ 1
Please note that all timing parameters as
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V4082
The pulldown
The type