mds108 Zarlink Semiconductor, mds108 Datasheet
mds108
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mds108 Summary of contents
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... Mbps auto-negotiating RMII ports • 1 10/100 Mbps auto-negotiating MII/serial port (port 8) that can be used as a WAN uplink 9th port • Operates stand-alone or can be cascaded with a second MDS108 to reach 16 ports - XLink expansion MII port (port 8) - Operates at 100/200/300/400 Mbps 2 • External I ...
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... Service/ Differentiated Services (TOS/DS) field. This priority can be defined as transmit and/or drop priority. The MDS108 can be used to create an 8-port unmanaged switch with one WAN router port by connecting a CPU (ARM or MPC 850) to the additional MII port (port 8). The only external components needed are the physical layer transceivers and a single SBRAM, resulting in a low, total system cost ...
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... MDS108 Physical Pinout 208 206 204 202 200 198 196 L_A[7] L_A[ VDD_CORE L_A[9] 4 L_A[10] Pin 1 I.D. L_A[11] 6 VSS L_A[12] 8 L_A[13] 10 L_A[14] VDD VSS (CORE) 18 M0_TXEN M0_TXD[0] 20 M0_TXD[1] M0_CRS_DV 22 M0_RXD[0] M0_RXD[1] 24 VDD M1_TXEN 26 M1_TXD[0] 28 M1_TXD[1] M1_CRS_DV 30 M1_RXD[0] M1_RXD[1] ...
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... VSS (CORE) 19 M0_TXEN 20 M0_TXD[0] 21 M0_TXD[1] 22 M0_CRS_DV 23 M0_RXD[0] 24 M0_RXD[1] 25 VDD 26 M1_TXEN 27 M1_TXD[0] 28 M1_TXD[1] 29 M1_CRS_DV 30 M1_RXD[0] 31 M1_RXD[1] 32 VSS 33 M2_TXEN 34 M2_TXD[0] MDS108 35 M2_TXD[1] 36 M2_CRS_DV 37 M2_RXD[0] 38 M2_RXD[1] 39 VDD (CORE) 40 M3_TXEN 41 M3_TXD[0] 42 M3_TXD[1] 43 M3_CRS_DV 44 M3_RXD[0] 45 M3_RXD[1] 46 VSS (CORE ...
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... TSTOUT[1] 133 TSTOUT[2] 134 TSTOUT[3] 135 TSTOUT[4] 136 TSTOUT[5] 137 TSTOUT[6] 138 TSTOUT[7] 139 T_MODE 140 VSS (CORE) 141 RSTOUT# MDS108 142 RSTIN# 143 MIRROR_CONTROL[0] 144 MIRROR_CONTROL[1] 145 MIRROR_CONTROL[2] 146 MIRROR_CONTROL[3] 147 VDD 148 SCLK 149 VSS 150 L_A[2] 151 ...
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... MDS108 Figure 2 - MDS108 Block Diagram 6 Zarlink Semiconductor Inc. Data Sheet ...
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... MDS108 is designed to support minimum interframe gaps between incoming packets. The Frame Engine (FE) is the primary packet buffering and forwarding engine within the MDS108. As such, the FE controls the storage of packets into and out of the external frame buffer memory, keeps track of frame buffer availability and schedules packet transmissions ...
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... The MDS108 allows the designer to set the high priority weight value between 1 and 15. If both queues contain packets, and the high priority weight is set to the value 4, then the MDS108 will transmit 4 high priority packets before transmitting each low priority packet. ...
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... Not surprisingly, packets designated high-drop are sacrificed with higher odds during congestion than packets designated low-drop. The following table summarizes the WRED operation of the MDS108. It lists the buffer thresholds at which each drop probability takes effect. WRED Threshold ...
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... Port-Based Prioritization Some applications may require an explicit prioritization of packets based upon the port the packet originates from. Defining specific ports of a switch Phone ports is a specific example that makes use of MDS108’s ability to assign default priorities to ports. The MDS108 can be configured to provide specific priority definitions four ports (ports 0 – 3). These user defined port priorities override the packet priority markings (VLAN tag or TOS/DS), and the new priority is applied to all packets that enter the switch from that port ...
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... Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the source MAC addresses of all packets received from the trunk are checked against the MCT database to ensure that they have a port Packets that have a port ID other than 0 and 1 will cause the MDS108 to learn the new MAC address for this port change. ...
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... Power Saving Mode in MAC The MDS108 was designed to be power efficient. When the internal MAC sections detect that the external port is not receiving or transmitting packets, it will shut off and conserve power. When new packet data is loaded into the output transmit FIFO of a MAC in power saving mode, the MAC will return to life and begin operating immediately. ...
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... L_A[10:9] provide the frequency of operation selection as shown in the table. When two MDS108 devices are cascaded to form a 16 port switch, the XLink port on each MDS108 is treated were a standard switch output. Standard Ethernet packet protocols are utilized, traditional packet integrity checks are performed at the receiving MDS108 XLink port, and standard length Ethernet packets are transmitted ...
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... Either a read or write command (see waveforms above). 4. Data to be written provided on DATA0, or data to be read provided on ACK. Any command can be aborted in the middle by sending an ABORT pulse to the MDS108. An ABORT pulse occurs when DATA is sampled low and STROBE is rising, followed by DATA being sampled high when STROBE falls. ...
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... Configuration Register Definitions The MDS108 registers can be accessed via the parallel interface and/or the I accessible through the parallel interface. The access method for each register is listed in the individual register definitions. Each register is 8 bits wide. 12.1 GCR - Global Control Register • Access: parallel interface, Write Only • ...
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... TOS[3:5]. 12.6 LPBT – Low Drop Precedence Buffer Threshold • Access: parallel interface and I • Address: h02 Bits [7:0] LOW_DROP_CNT MDS108 2 C, Read/Write Maximum number of multicast frames allowed to be buffered inside the device at any one time 2 C, Read/Write Buffer Low Threshold – the ...
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... Bit 4 Mapped priority of tag value 4 Bit 5 Mapped priority of tag value 5 Bit 6 Mapped priority of tag value 6 Bit 7 Mapped priority of tag value 7 MDS108 2 C, Read/Write Maximum number of flooded frames allowed within any time interval indicated by TimeBase bits (violations are discarded) 000 = 100 2s 001 = 200 2s 010 = 400 2s 011 = 800 2s 100 = 1 ...
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... Enable and configure port-based priorities for ports and 3 Bit 0 EN0 Port 0: Enable enabled Bit 1 P0 Port 0: Priority high low Bit 2 EN1 Port 1: Enable enabled Bit 3 P0 Port 1: Priority high low MDS108 2 C, Read/Write 2 C, Read/Write Read/Write 18 Zarlink Semiconductor Inc. Data Sheet (Default 0) (Default 0) ...
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... MII_OP0 – MII Register Option 0 • Access by parallel interface and I • Address: h0C Permits a non-standard address for the Phy Status Register. When low and high Address bytes are 0, the MDS108 will use the standard address. Bit [7:0] Low order address byte MDS108 2 C, Read/Write ...
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... Access: parallel interface and I • Address: h10 Bits [3:0] Port Mode Bit [3] Bit [2] Bit [1] Bit [0] Bits [6:4] PVID Bit [7] Reserved MDS108 2 C, Read/Write 2 C, Read/Write 2 C, Read/Write 2 C, Read/Write 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – ...
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... Bit [7] Reserved 12.23 ECR1P3 – Port 3 Control Register • Access: parallel interface and I • Address: h13 Bits [3:0] Port Mode MDS108 2 C, Read/Write 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – ...
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... ECR1P5 – Port 5 Control Register • Access: parallel interface and I • Address: h15 Bits [3:0] Port Mode Bit [3] Bit [2] MDS108 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 1 – Half Duplex 0 – Full Duplex 1 – ...
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... Address: h17 Bits [3:0] Port Mode Bit [3] Bit [2] Bit [1] Bit [0] Bits [6:4] PVID Bit [7] Reserved MDS108 1 – Half Duplex 0 – Full Duplex 1 – Flow Control Off 0 – Flow Control On Port-based VLAN Read/Write 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – ...
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... Flow control frame CRC byte 0 12.32 FC_3 – Flow Control CRC Byte 1 • Access: parallel interface and I • Address: h1C Bits [7:0] Flow control frame CRC byte 1 MDS108 2 C, Read/Write 1 – Force configuration based on Bits [2:0] 0 – Autonegotiate and advertise based on Bits [2:0] 1 – 10 Mbps 0 – 100 Mbps 1 – ...
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... CHECKSUM - EEPROM Checksum • Access: parallel interface and I • Address: h24 The calculation is [0x100 - ((sum of registers 0x00~0x23) & 0xFF)]. For example, based on the default register settings, the CHECKSUM value would be 0xEE. Bits [7:0] Checksum MDS108 2 C, Read/Write (Default 99 Read/Write (Default 9A Read/Write ...
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... MDS108 Pin Descriptions Note: # Active low signal I Input signal S Input signal with Schmitt-Trigger O Output signal OD Open-Drain driver I/O Input & Output signal SL Slew Rate Controlled D Pulldown U Pullup 5 5V Tolerance Pin No(s). Frame Buffer Memory Interface 201, 200, 199, 197, 196, 195, L_D[31:0] 193, 192, 191, 190, 188, 187, ...
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... Port 8 MII Interface 105, 104, 103, 102 M8_RXD[3:0] 113, 112, 111, 110 M8_TXD[3:0] 109 M8_TXEN 97 M8_RXDV 100 M8_RXCLK 107 M8_TXCLK MDS108 Symbol Type O Port 1 Transmit Data O Port 1 Transmit Enable I, U Port 2 Receive Data I, D Port 2 Carrier Sense and Data Valid O Port 2 Transmit Data ...
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... VDD 147, 152, 166, 175, 194, 202 18, 46, 80, 106, 140, 171, 198 VSS (Core) 7, 32, 66, 94, 99, 117, 121, VSS 149, 154, 162, 180, 189, 207 MDS108 Symbol Type I, U Port 8 Link Status I/O, U Port 8 Speed Select (100 ...
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... As an input, it provides a reference clock source to the Port 8 MAC when it is configured in speed-up mode • M8_REFCLK input frequency is equal to 25% of the Port 8 speed (data rate) Port 8 Configuration Mode Reg. 10/100 M 2x 200 M 3x 300 M 4x 400 M MDS108 Speed Input/Output Output Input Input Input 29 Zarlink Semiconductor Inc. Data Sheet M8_REFCLK Freq. M_CLK/2 ...
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... SBRAM Self Test Note 1: If the MDS108AL is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to load its configuration from the EEPROM. If the EEPROM is blank or not preset, it will not boot up. The parallel port can be used to program the EEPROM at any time. ...
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... I/O Capacitance I/O 6 Thermal resistance with 0 air flow ja Thermal resistance with 1 m/s air flow 6 ja Thermal resistance with 2 m/s air flow Thermal resistance between junction and case jc MDS108 -65GC to +150C -40C to +85C +125C + (VDD +3.3 V) -0.5V to (VDD +0 -40C to +85 C AMBIENT Min. 2.4 2.0 < VDD) IN < ...
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... Configuration Port 0-7 Port RMII 10/100 M MII 100 M RMII Not Used 100 M RMII 10/100 M MII 100 M RMII 200 M MII 100 M RMII 300 M MII 100 M RMII 400 M MII MDS108 (Hz 1. Input M_CLK SCLK M8_REF (RMII ...
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... L_D[31:0] input hold time L3 L_D[31:0] output valid delay L4 L_A[18:2] output valid delay L6 L_ADSC# output valid delay L8 L_WE# output valid delay L9 L_OE# output valid delay Table 4 - Frame Buffer Memory Interface Timing MDS108 L_D[31:0] Figure 5 - Frame Buffer Memory Interface Parameter Min. (ns Zarlink Semiconductor Inc ...
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... M8_TXCLK rise to M8_TXEN active delay 4 M8_TXCLK rise of last M8_TXD bit to M8_TXEN inactive delay 5 M8_TXCLK High wide 6 M8_TXCLK Low wide M8_TXCLK input rise time require M8_TXCLK input fall time require *Inf. = infinite MDS108 50 MHz Min. (ns Table 5 - RMII Timing Requirements Figure 6 - Transmit Timing ...
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... M8_RXDV High input setup time 8 M8_RXDV High input hold time 9 M8_RXCLK High wide 10 M8_RXCLK Low wide M8_RXCLK input rise time require M8_RXCLK input fall time require Table 7 - Receive Timing Requirements MDS108 Figure 7 - Receive Timing Time Min Zarlink Semiconductor Inc. ...
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... Pin 1 indicator may be a corner chamfer, dot or both. 2. Controlling dimensions are in millimeters. 3. The top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 4. Dimension D1 and E1 do not include mould protusion. c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. = 0° ...
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