adv101 Analog Devices, Inc., adv101 Datasheet - Page 5

• Manufacturer Part Number: adv101
• Description: Cmos 80 Mhz, Triple 8-bit Video Dac
• Manufacturer: Analog Devices, Inc.

REV. B
Pin
Mnemonic
BLANK
SYNC
CLOCK
REF WHITE
R0–R7,
G0–G7,
B0–B7
IOR, IOG, IOB
I
FS ADJUST
COMP
V
V
GND
SYNC
REF
AA
Function
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE cur-
rent source on the I
only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,
BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out-
puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched
on the rising edge of clock.
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular
PCB power or ground plane.
Red, green and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75
they are all being used.
Sync current output. This high impedance current source can be directly connected to the IOG output. This al-
lows sync information to be encoded onto the green channel. I
at logical zero. The amount of current output at I
If sync information is not required on the green channel, I
Full-scale adjust control. A resistor (R
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R
is given by:
The relationship between R
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 F ceramic capacitor
must be connected between COMP and V
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter-
nal resistor divider network is not recommended. A 0.1 F decoupling ceramic capacitor should be connected
between V
Analog power supply (5 V
Ground. All GND pins must be connected.
REF
and V
I
R
IOR, IOB (mA) = 8,628
SYNC
SET
SYNC
AA
.
( ) = 12,082
(mA) = 3,455
coaxial cable. All three current outputs should have similar output loads whether or not
output. SYNC does not override any other control or data input, therefore, it should
SET
SET
PIN FUNCTION DESCRIPTION
5%). All V
and the full-scale output current on IOG (assuming I
and the full-scale output current on IOR and IOB is given by:
SET
V
AA
V
REF
) connected between this pin and GND, controls the magnitude of the
REF
AA
pins on the ADV101 must be connected.
–5–
(V)/IOG (mA)
V
.
(V)/R
REF
SYNC
(V)/ R
SET
( )
while SYNC is at logical one is given by:
SET
SYNC
( )
SYNC
should be connected to AGND.
does not output any current while SYNC is
SYNC
is connected to IOG)
ADV101