SI52146-A01AGM SILABS [Silicon Laboratories], SI52146-A01AGM Datasheet - Page 17

• Manufacturer Part Number: SI52146-A01AGM
• Description: PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR
• Manufacturer: SILABS [Silicon Laboratories]

Pin #
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CKPWRGD_PDB
XIN/CLKIN
SDATA
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
DIFF4
DIFF4
DIFF5
DIFF5
XOUT
Name
SCLK
GND
VDD
VDD
VDD
VDD
VDD
OE0
OE1
Table 7. Si52146 32-Pin QFN Descriptions
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
Type
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
I, PU 3.3 V CMOS input. A real-time active low input for asserting power
PWR 3.3 V power supply
GND Ground for bottom pad of the IC.
I,PU
I,PU
I/O
O
I
I
SMBus compatible SCLOCK
down (PDB) and disabling all outputs (internal 100 k pull-up).
25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
25.00 MHz crystal input or 3.3 V, 25 MHz clock input
Refer to Table 1 on page 4 for OE specifications.
Refer to Table 1 on page 4 for OE specifications.
SMBus compatible SDATA
3.3 V input to disable DIFF0 (internal 100 k pull-up).
3.3 V input to disable DIFF1 (internal 100 k pull-up).
Preliminary Rev. 0.1
Description
Si52146
17