rf2059sr RF Micro Devices, rf2059sr Datasheet - Page 10

• Manufacturer Part Number: rf2059sr
• Description: High Performance Rf Pll/vco With Rf Mixers For Wlan Band Shifters
• Manufacturer: RF Micro Devices

RF2059
The RF2059 is a wideband RF frequency converter chip which includes a fractional-N phase-locked loop, a crystal oscillator cir-
cuit, a low noise VCO core, a LO signal multiplexer, two buffer circuits and two RF mixers. Synthesizer programming, device con-
figuration and control are achieved through a mixture of hardware and software controls. All on-chip registers are programmed
through a simple three-wire serial interface.
VCO
The VCO core in the RF2059 covers the frequency range 1550MHz to 2050MHz. It can be used in conjunction with the inte-
grated LO dividers to produce LO frequencies in the following three ranges:
VCO 2 must be selected by setting the PLL1x0:P1_VCOSEL and PLL2x0:P2_VCOSEL control words to 01. The VCO has 128
overlapping bands to achieve an acceptable VCO gain (20MHz/V nom) and hence a good phase noise performance across the
whole tuning range. The chip automatically selects the correct VCO band (“VCO coarse tuning”) to generate the desired LO fre-
quency based on the values programmed into the PLL1 and PLL2 registers banks. For information on how to program the
desired LO frequency into the PLL1 and PLL2 banks refer to page 11.
The automatic VCO band selection is triggered every time the ENBL pin is taken high. Once the band has been selected the PLL
will lock onto the correct frequency. During the band selection process fixed capacitance elements are progressively connected
to the VCO resonant circuit until the VCO is oscillating at approximately the correct frequency. The output of this band selection
is made available in the RB1:CT_CAL read-back register. A value of 127 or 0 in this register indicates that the selection was
unsuccessful, this is usually due to the wrong VCO being selected so the user is trying to program a frequency that is outside of
the VCO operating range. A value between 1 and 126 indicates a successful calibration, the actual value being dependent on
the desired frequency as well as process variation for a particular device. The band selection takes approximately 1500 cycles
of the phase detector clock (about 50us with a 26MHz clock). The band select process will center the VCO tuning voltage at
about 1.2V, compensating for manufacturing tolerances and process variation as well as environmental factors including tem-
perature. For applications where the synthesizer is always on and the LO frequency is fixed, the synthesizer will maintain lock
over a +/-60°C temperature range. However it is recommended to re-initiate an automatic band selection for every 30 degrees
change in temperature in order to maintain optimal synthesizer performance. This assumes an active loop filter. If start-up
time is a critical parameter, and the user is always programming the same frequency for the PLL, the calibration result may be
read back from the RB1:CT_CAL register, and written to the PLL1x2:P1_CT_DEF or PLL2x2:P2_CT_DEF registers (depending on
desired PLL register bank). The calibration function must then be disabled by setting the PLL1x0:P1_CT_EN and/or
PLL2x0:P2_CT_EN control words to 0. For further information please refer to the RF205x Calibration User Guide.
The LO divide ratio is set by the PLL1x0:P1_LODIV and PLL2x0:P2_LODIV control words.
The LO is routed to mixer1, mixer2, or both depending on the state of the MODE pin and the value of CFG1:FULLD.
The current in the VCO core can be programmed using the PLL1x3:P1_VCOI or PLL2x3:P2_VCOI control words. This allows opti-
mization of VCO performance for a particular frequency. For applications where the required LO frequency is above 2GHz it is
recommended that the LO buffer current be increased by setting CFG5:LO1_I and CFG5:LO2_I to 1100 (hex value C).
Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the VCO. The PLL includes automatic
calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock-time and noise
performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to
divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52MHz. The
reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set high for divider
bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2 (010) to 7 (111)
when the reference divider is enabled.
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VCO
2
VCO Frequency Range
1550MHz to 2050MHz
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at ([phone] or [e-mail].
Detailed Description
775MHz to 1025MHz
DIV 2
387.5MHz to 512.5MHz
DIV 4
DS100630