s3c2800 Samsung Semiconductor, Inc., s3c2800 Datasheet - Page 17

• Manufacturer Part Number: s3c2800
• Description: 32-bit Risc Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

PRELIMINARY DATA SHEET
POWER
VDD
VSS
AVDD
AVSS
VDD3OP
VSS3OP
PCI-BUS
PCI_AD[31:0]
PCI_C[3:0]/
nBE[3:0]
PCI_PAR
PCI_nFRAME
PCI_nTRDY
PCI_nIRDY
PCI_nSTOP
PCI_nDEVSEL
PCI_IDSEL
PCI_nPERR
PCI_nSERR
PCI_nLOCK
PCI_nREQ1
Signal
I/O
I/O PCI Address/Data Bus. Multiplexed address and data bus.
I/O PCI C (bus command) or Byte enables.
I/O PCI-parity. Parity is even across PCI_AD[31:0] and PCI_C[3:0]/nBE[3:0]. PCI_PAR is
I/O PCI_nFRAME is driven by the current PCI bus master to indicate beginning and
I/O The target of the current PCI transaction drives PCI_nTRDY. Assertion of
I/O The current PCI bus master drives PCI_nIRDY. Assertion of PC_nIRDY
I/O The target of the current PCI transaction may assert PCI_nSTOP to indicate to the
I/O The target of the current PCI transaction drives PCI_nDEVSEL. A PCI target
I/O PCI_nPERR is used for reporting data parity errors on PCI transactions.
I/O PCI_nSERR is used for reporting address parity errors or catastrophic failures
I/O When internal arbiter is used, PCI_nREQ1 is input mode.
P
P
P
P
P
P
I
S3C2800 core logic V
S3C2800 core logic V
S3C2800 Analog logic (PLL loop filter) V
S3C2800 Analog logic (PLL loop filter) V
S3C2800 GPIO port V
S3C2800 GPIO port V
valid one cycle after either an address or data phase. The PCI device that drives
PCI_AD[31:0] is responsible for driving PCI_PAR on the next PCI bus clock.
duration of a PCI access.
PCI_nTRDY indicates that the PCI target is ready to transfer data.
indicates that the PCI initiator is ready to transfer data.
requesting PCI master that it wants to end the current transaction.
asserts PCI_nDEVSEL when it decodes an address and command encoding, and
claims the transaction.
PCI_IDSEL is used during configuration cycles to select the PCI slave interface for
configuration.
PCI_nPERR is driven active by the device receiving PCI_AD[31:0],
PCI_C[3:0]/nBE[3:0], and PCI_PARITY, two PCI clocks following the data in which
bad parity is detected.
detected by a PCI target.
PCI_nLOCK indicates an atomic operation to a bridge that may require multiple
transactions to complet. When PCI_nLOCK is asserted, non-exclusive transactions
may proceed to a bridge that is not currently locked. A grant to start a transaction on
PCI does not guarantee a control of PCI_nLOCK. Locked transactions may be
initiated only by the host bridges.
or when external arbiter is used, PCI_nREQ1 is output mode.
Table 3. S3C2800 Signal Descriptions (Continued)
DD
SS
DD
SS
.
.
(1.8 V).
(3.3 V).
Description
DD
SS
.
(1.8V).
S3C2800 MICROCONTROLLER
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