z86l0408ssc ZiLOG Semiconductor, z86l0408ssc Datasheet - Page 20

• Manufacturer Part Number: z86l0408ssc
• Description: Z8 8-bit Cost-effective Microcontrollers
• Manufacturer: ZiLOG Semiconductor

FUNCTIONAL DESCRIPTION (Continued)
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timer and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-
tive. The device is recovered by interrupts, either external-
ly or internally generated. An interrupt request must be ex-
ecuted (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10 A. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low condition
on pin P27 releases the STOP mode even if P27 is an out-
put. Program execution begins at location 000C(Hex).
However, when P27 is used to release the STOP mode,
the I/O port mode registers are not reconfigured to their de-
fault power-on conditions. This prevents any I/O, config-
ured as output when the STOP instruction was executed,
from glitching to an unknown state. To use the P27 release
approach with STOP mode, use the following instruction:
LD
NOP
STOP
Notes:
X = Dependent on user’s application.
Stop-Mode Recovery pin P27 is not edge triggered.
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, such as:
FF
6F
or
FF
7F
20
NOP
STOP
NOP
HALT
P2M, #1XXX XXXXB
; clear the pipeline
; enter STOP mode
; clear the pipeline
; enter HALT mode
P R E L I M I N A R Y
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0. WDT = 5F (Hex)
Opcode WDT (5FH). The first time opcode 5FH is execut-
ed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T
plus 18 XTAL clock cycles. The internal RC driven WDT
does not run in stop mode, unless the permanent WDT en-
able option is selected. The WDT does not run in halt
mode unless WDH instruction is executed or permanent
WDT enable option is selected.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Note: Opcode WDH and permanently enabled WDT is
not directly supported by the Z86CCP00ZEM.
WDT Clock Source. The WDT clock source option selects
the clock source for the WDT. It can be the internal on-
board RC oscillator or the internal system clock (SCLK). If
the SCLK is selected, then the WDT time out (T
130,416 x SCLK and the T
the permanent WDT option is selected in this case; the
WDT will not run in STOP mode. (Z86L04 only)
Auto Reset Voltage (V
in. The auto-reset circuit resets the Z8 when it detects the
V
versus temperature.
CC
below V
LV
. Figure 17 shows the Auto Reset Voltage
LV
). The Z8 has an auto-reset built-
POR
is 16,362 x SCLK. Also, if
DS97LVO0901
WDT
Zilog
WDT
POR
) is
;
,