s3455 Applied Micro Circuits Corporation (AMCC), s3455 Datasheet

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s3455

Manufacturer Part Number
s3455
Description
Sonet/sdh/atm Oc-48 4-bit Transceiver With Cdr
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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Part Number:
s3455PB
Manufacturer:
AMCC
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S3455
SONET/SDH/ATM OC-48 4-Bit Transceiver with CDR
Features
• CMOS 0.18 micron technology
• Complies with Bellcore and ITU-T specifica-
• On-chip high-frequency PLL for clock genera-
• Supports OC-48 (2488.32 Mbps) with FEC
• Reference frequency of 155.52 MHz to 166.62
• Interface to LVDS and LVCMOS logic
• 4-bit LVDS data path
• 196 Pin PBGA
• Diagnostic loopback mode
• Supports line timing
• Lock detect
• Signal detect input
• Low jitter LVDS interface
• Internal FIFO to decouple transmit clocks
• Single 1.8 V supply
• Typical power under 1.0 W
Applications
• Wavelength Division Multiplexing (WDM)
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
tions
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Description
The S3455 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-48 (2.488 Gbps – 2.670 Gbps) interface
device. The S3455 receives an OC-48 scrambled
Non-Return to Zero (NRZ) signal and recovers
the clock from the data. The chip performs all
necessary serial-to-parallel and parallel-to-serial
functions in conformance with SONET/SDH
transmission standards. The device is suitable
for SONET-based WDM applications. Figure 1
shows a typical network application.
On-chip clock synthesis is performed by the
high-frequency Phase-Locked Loop (PLL) on the
S3455 transceiver chip allowing the use of a
slower external transmit clock reference. The
chip can be used with a 155.52 MHz (or
166.62 MHz) reference clock in support of
existing system clocking schemes.
The low jitter LVDS interface is compliant with
the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3455 is packaged in a
196 Pin PBGA, offering designers a small
package outline.
Overview
The S3455 transceiver implements SONET/SDH
serialization/deserialization, and transmission
functions. The block diagram in Figure 2 of the
S3455 Data Sheet shows the basic operation of
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System Block Diagram with the S3455
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the chip. This chip can be used to implement
the front end of SONET equipment, which
consists primarily of the serial transmit interface
and the serial receive interface. The chip
handles all the functions of these two elements,
including parallel-to-serial and serial-to-parallel
conversion, clock generation, and system
timing. The system timing circuitry consists of
management of the data stream and clock
distribution throughout the front end. The table
below shows the suggested interface devices
for the S3455.
AMCC Suggested Interface Devices
The S3455 is divided into a transmitter section
and a receiver section. The sequence of
operations is as follows:
Transmitter Operations
Receiver Operations For One Channel
Internal clocking and control functions are
transparent to the user.
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• 4-bit parallel input
• Parallel-to-serial conversion
• Serial output
• Clock and data recovery from serial input
• Serial-to-parallel conversion
• 4-bit parallel output
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STS-192 POS/ATM SONET/SDH Mapper
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s3455 Summary of contents

Page 1

... The low jitter LVDS interface is compliant with • SONET/SDH test equipment the bit-error rate requirements of the Bellcore • ATM over SONET/SDH • Section repeaters and ITU-T standards. The S3455 is packaged in a • Add Drop Multiplexers (ADM) 196 Pin PBGA, offering designers a small • Broad-band cross-connects package outline. ...

Page 2

... AMCC is a registered trademark of Applied Micro Circuits Corporation. PowerPC and the PowerPC logo are registered trademarks of IBM Corporation. All other trademarks are the www.amcc.com property of their respective holders. Copyright © 2006 Applied Micro Circuits Corporation. All Rights Reserved. S3455_PB2022_v1.01_20061016 SPECIFIC AT IONS ...

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