msm8128vlmb-85 MOSA electronics corp., msm8128vlmb-85 Datasheet - Page 7

• Manufacturer Part Number: msm8128vlmb-85
• Description: 128k Sram
• Manufacturer: MOSA electronics corp.

MSM8128 - 70/85/10/12
Low V
Low V
AC Characteristics Notes
(1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among
(2) t
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state.
(5) OE is continuously low. (OE=V
(6) Dout is in the same phase as written data of this write cycle.
(7) Dout is the read data of next address.
(8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be
(9) t
CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2
going low and WE going high. t
applied to I/O pins.
levels. These parameters are sampled and not 100% tested.
WR
WHZ
CC
CC
is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle.
is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage
Data Retention Timing Waveform 1 (CS1 controlled)
Data Retention Timing Waveform 2 (CS2 controlled)
Vcc
CS2
Vcc
CS1
V
V
4.5V
0.4V
0V
4.5V
2.2V
0V
DR2
DR
t
CDR
IL
t
WP
CDR
)
is measured from the beginning of write to the end of write.
DATA RETENTION MODE
DATA RETENTION MODE
CS1 Vcc-0.2V
CS2
0.2V
t
R
t
R
4.5V
2.2V
4.5V
Issue 4.5 : April 2001