74HCT14D,653 NXP Semiconductors, 74HCT14D,653 Datasheet - Page 10

IC TRIGGER SCHM HEX INVRT 14SOIC

74HCT14D,653

Manufacturer Part Number
74HCT14D,653
Description
IC TRIGGER SCHM HEX INVRT 14SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT14D,653

Number Of Circuits
6
Logic Type
Inverter with Schmitt Trigger
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Inputs
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
HCT
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1515-2
74HCT14D-T
933714440653

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HCT14D,653
Manufacturer:
NEXPERIA/安世
Quantity:
20 000
NXP Semiconductors
15. Application information
74HC_HCT14
Product data sheet
Fig 11. Typical 74HCT transfer characteristics
(mA)
a. V
I
1.5
CC
1.2
0.9
0.6
0.3
0
0
CC
= 4.5 V
1
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
P
Average ΔI
and
An example of a relaxation circuit using the 74HC14; 74HCT14 is shown in
2
add
P
f
t
t
ΔI
i
r
f
add
= input frequency (MHz);
= fall time (ns); 90 % to 10 %;
= rise time (ns); 10 % to 90 %;
CC(AV)
Figure
= f
= additional power dissipation (μW);
i
3
× (t
= average additional supply current (μA).
CC(AV)
13.
r
× ΔI
All information provided in this document is subject to legal disclaimers.
4
CC(AV)
differs with positive or negative input transitions, as shown in
V
mna849
I
(V)
Rev. 4 — 17 January 2011
5
+ t
f
× ΔI
CC(AV)
) × V
(mA)
I
CC
b. V
1.8
1.5
1.2
0.9
0.6
0.3
CC
0
0
CC
where:
= 5.5 V
1
74HC14; 74HCT14
2
Hex inverting Schmitt trigger
3
4
© NXP B.V. 2011. All rights reserved.
5
mna850
V
Figure
I
(V)
Figure 12
6
14.
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