mu9c4485a Music Semiconductors, Inc., mu9c4485a Datasheet - Page 21

• Manufacturer Part Number: mu9c4485a
• Description: Wideport Lancam? Family
• Manufacturer: Music Semiconductors, Inc.

Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
Section under the tELEH parameter. For two cycle TCO reads of a register’s contents, the first cycle (Command
Write TCO) is short, and the second cycle (Command read) is medium.
LENGTH
Medium
CYCLE
Short
Long
Note: D15 reads back as 0.
Note: D15, D10, D5, and D2 read back as 0s. Reserved locations D14, D12, D9, D7, D4, and D1 should always
Chng.
Limits
be set to 0.
RST
Dest.
Seg.
Set
15
= 0
= 1
15
No
R
S
E
E
T
=
0
Match Flag
14
No Change
Command Write
MOV reg, reg (except L-70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC, NOP
SFT (A
MOV reg, reg (L-70)
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
SFT (L)
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
VBC (NFA valid)
14
0
Disable
Enable
= 01
= 11
=00
Count
Dest.
Start
Limit
)
13
13 12
No Change
Full Flag
12
0
Disable
Enable
= 00
= 01
= 11
Table 10: Segment Control Register Bit Assignments
INSTRUCTION SET SUMMARY Continued
Count
Dest.
Limit
11
End
11
Table 9: Control Register Bit Assignments
REGISTER BIT ASSIGNMENTS
Translation
No Change
10
Translated
Translated
Source
Chng.
Input Not
Limits
Seg.
Set
= 0
= 1
10
No
Table 8: Instruction Cycle Lengths
Input
= 00
= 01
= 11
9
0
9
Command Read
Status register or
16-bit register
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
64 CAM/0 RAM = 000
Count
CAM/RAM Part.
Start
8
Src.
Limit
No Change = 111
8
21
CYCLE TYPE
7
0
7
6
Count
Src.
Limit
End
6
WidePort LANCAM
Comp. Mask
Data Write
Comparand register
Mask register
Memory array
Memory array
Comparand register
Mask register
Count
Chng.
Dest.
No Change
Load
Seg.
5
None = 00
(NFA invalid)
(NFA valid)
(last segment)
(last segment)
(not last segment)
(not last segment)
MR1 = 01
MR2 = 10
= 0
= 1
No
5
= 11
0
4
4
AR Inc/Dec
Count
Value
Dest.
No Change
3
Decrement
Seg.
Increment
Disable
3
= 00
= 01
= 10
= 11
Count
Chng.
Load
Seg.
Src.
= 0
= 1
No
2
2
Data Read
Comparand register
Mask register
Memory array
Enhanced Mode
Standard Mode
1
No Change
Reserved
0
1
Mode
= 00
= 01
= 10
= 11
®
Count
Family
Value
Seg.
Src.
0
0
Rev. 2