pe3240 Peregrine Semiconductor Corp., pe3240 Datasheet - Page 9

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pe3240

Manufacturer Part Number
pe3240
Description
2.2 Ghz Ultracmos? Integer-n Pll For Low Phase Noise Applications
Manufacturer
Peregrine Semiconductor Corp.
Datasheet
Interface Mode
PE3240
Product Specification
Table 7. Primary Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
Table 8. Enhancement Register Programming
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Figure 7. Serial Interface Mode Timing Diagram
Document No. 70-0034-02 │ www.psemi.com
Interface
Serial*
Serial*
Mode
Sdata
E_WR
Sclk
S_WR
Enh
1
Enh
0
R
B
MSB (first in)
5
0
Reserved
R
B
4
1
B
0
MSB (first in)
M
B
2
8
t
DSU
M
B
3
Reserved
7
t
EC
B
Pre_en
1
B
4
M
B
t
DHLD
5
6
f
p
M
Output
B
6
B
5
2
M
B
7
4
M
B
8
3
Power
down
B
3
M
B
9
2
t
ClkH
M
B
10
1
©2006 Peregrine Semiconductor Corp. All rights reserved.
Counter
B
load
M
B
11
0
4
t
ClkL
B
R
12
3
B
R
13
2
output
MSEL
B
5
B
R
14
1
t
CWR
t
CE
B
R
15
0
f
c
(last in) LSB
output
B
A
B
16
3
6
t
PW
(last in) LSB
B
A
17
t
2
WRC
Page 9 of 12
B
Reserved
A
18
1
B
7
B
A
19
0

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