sh6614d SinoWealth Micro-Electronics Corp. Ltd, sh6614d Datasheet - Page 24

• Manufacturer Part Number: sh6614d
• Description: 4k 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

12. Interrupt
4 interrupt sources are available on SH6614D:
The configuration of system register $0:
12.1. External Interrupt ( INT0 )
External interrupt is shared with the PA.0, falling edge active. When the bit 3 of the register $0 (IEX) is set to 1, the external
interrupt is enabled, writing a "0" to PA.0 will generate an external interrupt.
12.2. Timer 0 interrupt, Base timer interrupt, Port interrupt ( INT1 )
If Iex = 1 then all valid interrupt requests will cause an interrupt. The overflow of timer 0 will create the interrupt of timer 0.The
overflow of the Base timer will create the interrupt of the Base timer. The falling edge of every port in PORTB will create INT1
interrupt (The condition is that the other port must be input/output high level).
12.3. The Enable flags and Request flags
Both the Enable flags and Request flags can be read or written by the software.
But the Request flags will be set "1" by the hardware interrupt and the Enable flags will be reset by the hardware when the
interrupt service routine is entered.
12.4. Interrupt Servicing Sequence Diagram:
In SH6610C CPU interrupt services routine, the user can enable any interrupt enable flag before returning from an interrupt. The
frequently asked question is when the next interrupt would be serviced? Will the nesting interrupt happen? From the servicing
sequence timing diagram, if interrupt request is ready and instruction execution N is IE enable. Then the interrupt can start right
after the next two instructions: I1 or instruction I2 disable the interrupt request or enable flag, then interrupt service sequence
would be terminated.
- External interrupt ( INT0 )
- Timer0 interrupt
- Base timer interrupt
- Port's falling edge detection interrupt ( INT1 )
Address
$00
$01
Inst. cycle
IRQX
Bit 3
IEX
Interrupt Generated
IRQT0
Bit 2
IET0
Instruction
Execution
N
1
IRQBT
IEBT
Bit 1
Interrupt Accepted
Instruction
Execution
IRQP
Bit 0
I1
IEP
2
24
Vector Generated
Stacking
1: Enable / 0: Disable
1: Request / 0: No request
Instruction
Execution
I2
3
Function
Fetch Vector address
Reset IE.X
4
Start at vector address
5
SH6614D