sh6613d SinoWealth Micro-Electronics Corp. Ltd, sh6613d Datasheet - Page 4

• Manufacturer Part Number: sh6613d
• Description: 4k 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

3. RAM
Built-in SRAM contains general-purpose data memory, LCD RAM, and system registers. They can be accessed by direct
addressing in one instruction.
The following is the memory allocation map:
$000~$01F: System register and I/O;
$300~$321, $350~$36D: LCD RAM space (34×4 bits).
The configuration of system register
*System Register $00~$12 refer to "SH6610C User manual".
Address
$06~$07
$0A
$0B
$0C
$0D
$0E
$1A
$1B
$1C
$1D
$1E
$00
$01
$02
$03
$04
$05
$08
$09
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1F
PACR.3
PBCR.3
PPULL
BTM.3
TM0.3
TBR.3
T0H.3
OCT1
C2.11
OCT2
T0L.3
VOL1
IRQX
INX.3
DPL3
LPS1
SEL1
PA.3
PB.3
OXS
C1.3
C2.3
C2.7
LPD
Bit3
IEX
-
-
-
-
-
-
PACR.2
PBCR.2
DPM.2
IRQT0
BTM.2
DPH.2
TM0.2
TBR.2
T0H.2
PAM2
T0L.2
C2.10
C2.14
VOL0
INX.2
DPL2
LPS0
SEL0
IET0
PA.2
PB.2
C1.2
C2.2
C2.6
Bit2
C1.6
O/S
-
-
-
-
-
LCDOFF
PACR.1
PBCR.1
CH2EN
IRQBT
DPM.1
BTM.1
DPH.1
TM0.1
TBR.1
T0H.1
PAM1
T0L.1
C2.13
DPL1
IEBT
PC.1
INX1
OXM
PA.1
PB.1
C1.1
C2.1
C2.5
C2.9
C2M
Bit1
C1.5
-
-
-
-
$020~$1FF: Data memory (480×4bits,partitioned into 4 banks).
PACR.0
PBCR.0
Should
CH1EN
set ”1”
BTM.0
DPM.0
DPH.0
OXON
TM0.0
T0H.0
TBR.0
C2.12
T0L.0
INX.0
DPL0
IRQP
PA.0
PB.0
PC.0
HLM
C1.0
C1.4
C2.0
C2.4
C2.8
C1M
Bit0
IEP
be
-
-
-
-
Interrupt enable flags
Interrupt request flags
Timer0 mode register
Base timer mode register
Timer0 load/counter low nibble
Timer0 load/counter high nibble
Reserved
PORTA
PORTB
Bonding option
Set PORTA to be output port
Set PORTB to be output port
Reserved
Table branch register
Data pointer for INX low nibble
Data pointer for INX middle nibble
Data pointer for INX high nibble
Bit1,2:PA.1 & PA.2 as PSG output or I/O PORT
Bit0:Heavy load mode
Bit3:Port pull-up control
Bit0:Turn on OSCX oscillator
Bit1:CPU clocks select (1:OSCX/0:OSC)
Bit3:OSCX type selection
Bit0: Programmer should be set “1”
Bit1:LCD off
Bit2,3:LCD frequency control
Bit2:Set LCD segment as output
Bit3:LCD Power degrade
PSG channel 1 low nibble
PSG channel 1high nibble
Bit3:channel 1 octave shift control
PSG channel 2 nibble 1 or alarm output
PSG channel 2 nibble 2
PSG channel 2 nibble 3
PSG channel 2 nibble 4
Bit3:channel 2 octave shift control
Bit0,Bit1:Channel 1,2 enable
Bit2,Bit3:volume control
Bit0,1:PSG1,PSG2 mode control
Bit2,3:PSG1,PSG2 clock source selection
Reserved
Index register(INX)
4/33
Function
01(default)
Initial
Value
0000
0000
0000
0000
0000
0000
0000
0000
0000
SH6613D
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
V1.0
W
W
W
W
W
W
W
W
W
W
R
-
-
-