sh6611a SinoWealth Micro-Electronics Corp. Ltd, sh6611a Datasheet - Page 3

• Manufacturer Part Number: sh6611a
• Description: 1k 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

Functional Description
1. CPU
The CPU contains the following function blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPM, and DPL), and Stacks.
1.1 PC (Program Counter)
The PC is used to address 1K Programmable ROM. It
consists of 12-bits:
Page Register (PC11), and Ripple Carry Counter (PC10 -
PC0).
The program counter normally increases by one (+1) with
every execution of an instruction except in the following
cases:
(1) When executing a jump instruction (such as JMP, BA0,
BC);
(2) When executing a subroutine call instruction (CALL);
(3) When an interrupt occurs;
(4) When the chip is at the INITIAL RESET mode.
The program counter is loaded with data corresponding to
each instruction.
1.2 ALU and CY
ALU performs arithmetic and logic operations.
The ALU provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI,
SBI)
Decimal adjustment for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decision (BA0, BA1, BA2, BA3, BAZ, BC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow, which the
arithmetic operation generates. During an interrupt service
or call instruction, the carry flag is pushed into the stack
2. ROM
The SH6611A can address 1K × 16 bit words of program area from $000 to $3FF.
ROM SPACE in the system is 1024 X 16 bits.
(a) Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
*JMP instruction can be replaced by any instruction.
(b) Table Data Reference
Table Data can be stored in the program memory and can be referenced by using the Table Branch (TJMP) and the Return
Constant (RTNW) instructions. The Table Branch Register (TBR) and Accumulator (A) are placed by an offset address in
program ROM. TJMP instruction branch into address ((PC11 - PC8) X (2
RTNW to return look-up value into (TBR, A). ROM code bit7-bit4 is placed into TBR and bit3-bit0 into A.
Address
000H
001H
002H
003H
004H
JMP instruction
JMP instruction
JMP instruction
JMP instruction
JMP instruction
Instruction
3/25
and restored back from the stack by the RTNI instruction. It
is unaffected by the RTNW instruction.
1.3 Accumulator
Accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with ALU, data
transfers between the accumulator and system register or
data memory can be performed.
1.4 Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range can have
3FFH locations. Pseudo index address (INX) is used to
read or write Data memory, then RAM address bit9 - bit0
comes from DPH, DPM and DPL.
1.5 Stack
This group of registers used to save the contents of CY &
PC (11-0) sequentially with each subroutine call or
interrupt. It is organized 13 bits X 4 levels. The MSB is
saved for CY. 4 levels are the maximum allowed total for
subroutine calls and interrupts.
Note:
The contents of Stack are returned sequentially to the PC
with the return instructions (RTNI/RTNW). Stack is
operated on a first-in, last-out basis. This 4-level nesting
includes both subroutine calls and interrupts requests.
Note that program execution may enter an abnormal state
if the number of calls and interrupts requests exceeds 4,
then the bottom of stack will be shifted out.
Jump to RESET service routine
Jump to External interrupt service routine
Jump to TIMER0 service routine
Jump to TIMER1 service routine
Jump to PB service routine (PORTB)
8
) + (TBR, A)). The address is determined by
Remarks
SH6611A
Ver 0.0