sh66k12 SinoWealth Micro-Electronics Corp. Ltd, sh66k12 Datasheet - Page 11

• Manufacturer Part Number: sh66k12
• Description: Mask 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

7. Interrupt
Four interrupt sources are available on SH66K12:
- External interrupt ( INT share with PA.0)
- Timer0 interrupt
- Timer1 interrupt
- Port’s falling edge detection interrupt ( PB )
(a) Interrupt Control Bits and Interrupt Service:
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by program.
Those flags are cleared to 0 at initialization by chip reset.
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources.
(b) Interrupt Servicing Sequence Diagram:
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any INTERRUPT enable flag before returning from the
interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt
request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two
instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt
service will be terminated.
(c) External Interrupt ( INT )
External interrupt is shared with the bit0 of PORTA. When bit3 of system register 0 (IEX) is set to 1, the external interrupt will be
enabled, and a falling edge signal on PA.0 will generate an external interrupt. (Note: while external interrupt is enabled, writing
a “0” to bit0 of PORTA will generate an external interrupt).
8. System Clock
SH66K12 has one clock source. OSC is 32.768KHz crystal or 262KHz RC determined by code option. The OSC generates the
basic clock pulses that provide the system clock to supply CPU and on-chip peripherals (TIMER0, TIMER1, LCD).
Address
Inst. cycle
$00
$01
IEX
IRQX
Bit3
Interrupt Generated
Instruction
Execution
N
1
IET0
IRQT0
Bit2
Interrupt Accepted
Instruction
Execution
I1
IET1
IRQT1
2
Bit1
Vector Generated
Stacking
IEP
IRQP
Instruction
Execution
Bit0
11
I2
3
Fetch Vector address
Reset IE.X
interrupt enable flags
interrupt request flags
4
Remarks
Start at vector address
5
SH66K12