sh6631a SinoWealth Micro-Electronics Corp. Ltd, sh6631a Datasheet
sh6631a
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sh6631a Summary of contents
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... External interrupts: PortB & PortC (Falling edge). General Description SH6631A is dedicated to infrared remote control transmitter applications. This chip integrates the SH6610C 4-bit CPU core with SRAM, program ROM, an 8-bit timer, and programmable input/output driving buffers and carrier synthesizer. The standby function, which can be used to stop/start the ceramic resonator oscillation, facilitating the low power dissipation of the system. ...
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... Reset input (active low). Bit programmable I/O pin shared with external event counter input T0. Bit programmable I/O pins. Bit programmable I/O pins, Vector Interrupt (Active falling edge). 2 CPU PORTA (4 BITS) PORTA [1:3] PORTB (4 BITS) PORTB [0:3] PORTC (4 BITS) PORTC [0:3] PORTD (2 BITS) PORTD [0:1] REMOTE CONTROL SYNTHESIZER REM Descriptions SH6631A ...
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... Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) 2. ROM The SH6631A can address 1024 X 16 bit of program area from $000 to $3FF. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address ...
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... T0S T0E SH6631A Description Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Reserved Timer0 load/counter register low digit Timer0 load/counter register high digit Reserved Reserved PORTA PORTB PORTC PORTD Reserved REM Data Output Table Branch Register Pseudo index register ...
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... The timer overflow will generate an internal interrupt request when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will start. This can also be used to wake CPU from HALT mode. High nibble first; Followed by Low nibble. Load Reg. L 8-bit timer counter Latch Reg. L Figure. 1 Timer Load register Configure 5 SH6631A Load Reg. H ...
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... Bit1 Bit0 - T0S T0E 0 OSC PA.0/T0 1 T0E T0S TM0 [2:0] Figure. 2 Time related withT0 6 Ratio N 2048 (initial) 512 128 R/W Remarks Bit0: T0 signal edge W Bit1: T0 signal source TIMER0 (8bits) 3 SH6631A ...
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... I/O PORT The SH6631A provides 14 I/O pins. Each I/O pin contains pull-up MOS controllable by the program. When every I/O is used as an input port, the port control register (PCR) controls ON/OFF of the output buffer. Sections below show the circuit configuration of I/O ports. PORTA, PORTB, PORTC and PORTD Each of these ports contains 4 bit I/O pins (PortD contains 2 bit I/O pins) ...
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... PB0OUT PORTA.3 PA3OUT PORTA.2 PA2OUT PORTA.1 PA1OUT PORTC.0 PC0OUT PORTB.3 PB3OUT PORTB.2 PB2OUT PORTB.1 PB1OUT PORTB.0 PB0OUT FALLING EDGE DETECTION Default: opt_pint = 0 FALLING EDGE DETECTION Option set: opt_pint = 1 Figure. 4 PORT Interrupt Block Diagram 8 SH6631A to GND will DD . The DD PORT INTERRUPT PORT INTERRUPT ...
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... Remote Control Synthesizer SH6631A builds-in a carrier synthesizer for infrared or RF remote control circuits. Address Bit3 Bit2 $0D - $13 PPULL CPS CPS: Oscillator Range Selection 0: 455K Hz (default) 1: 3.64M Hz CF1-0: Carrier Frequency Control carrier (default /8, 1/2 duty fx/12, 1/3 duty 1, 1: fx/12, 1/2 duty REMO: REM output pin data control. ...
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... The System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals Instruction cycle time: (1) 4/455KHz ( ≈ 8.79µs) for 455KHz system clock. (2) 4/4MHz ( = 1µs) for 4MHz system clock. Oscillator (1) Ceramic resonator: 400KHz - 4MHz. (2) External input clock: 30KHz - 4MHz. 10p - 200p OSCI C Ceramic C OSCO 10p - 200p OSCI External clock source OSCO 10 SH6631A GND ...
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... However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated. 9. HALT and STOP mode After the execution of HALT instruction, SH6631A will enter HALT mode. In HALT mode, the CPU will stop operating; however, the peripheral circuit (timer) will keep operating. After the execution of STOP instruction, SH6631A will enter STOP mode. ...
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... Bit1 Bit0 R/W LPD1 LPD0 W 12 ≤ LPDL : Power rise LPD-detect voltage. LPDH is reached LPDX ＞ without any delay then cancel the DD LPDH Remarks LPD Enable Control (LPD3 ~ 0): 0101: LPD Enable (Power-on initial) 1010: LPD Disable SH6631A ≦ LPDL ...
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... Power-on reset 3. Low Power Detection reset Program counter CY Data memory System register AC Timer counter Timer load register LPD I/O ports PPULL CPS CF1 CF0 T0S T0E REMO Hardware 13 After power-on reset $000 Undefined Undefined Undefined Undefined 0 0 0101 Input SH6631A ...
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... AC, Mx ← AC, Mx ← Mx ⊕ I AC, Mx ← AC, Mx ← Mx & I Function AC; Mx ← Decimal adjust for add. AC; Mx ← Decimal adjust for sub. Function ← ← AC, Mx ← SH6631A Flag Change Flag Change CY CY ...
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... CY ← X (Not include p) PC ←ST; TBR ← hhhh; PC ←llll AC CY; PC ← ← X (Include p) PC ← (PC11-PC8) (TBR) (AC) No Operation I Immediate data ⊕ Logical exclusive OR | Logical OR & Logical AND bbb RAM bank = 000 TBR Table Branch Register 15 SH6631A Flag Change CY ...
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... OSCI (Driven with external clock, for reference) µ A I/O ports 3.0V I/O µ RESET µ A I/O ports with pull-up GND I/O µ A I/O ports with no pull-up; V I/O µ A For OSCI µ GND + 0.25 (With pull-up) RESET µ GND + 0.25 (No pull-up) RESET V I/O ports -1.0mA OH V I/O ports 5mA OL ms Ceramic Oscillator = 455KHz SH6631A = GND ...
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... OSCI (Driven with external clock, for reference) µ A I/O ports 3.0 I/O µ RESET µ A I/O ports with pull-up GND I/O µ A I/O ports with no pull-up; V I/O µ A For OSCI µ GND + 0.25 (With pull-up) RESET µ GND + 0.25 (No pull-up) RESET V I/O ports -1.0mA OH V I/O ports 5mA OL SH6631A = GND ...
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... T T0 Input Width IW T High Pulse Width IWH T Low Pulse Width IWL Timing Waveform RESET OSC Min. Typ. Max. Unit 1.7 2.1 2.0 3.5 Min. Typ. Max. Unit 40/N) CY 1/ OSC1 18 Condition 2 3 µ A Condition µ Prescaler divide ratio ns ns SH6631A ...
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... PORTB.0 PORTA.3 20p OSCO PORTA.2 PORTA.1 OSCI PORTA.0 20p V DD PORTD.1 PORTD.0 GND PORTC.3 PORTC.2 PORTC.1 R1 REM PORTC.0 PORTB.3 PORTB.2 PORTB.1 RESET PORTB.0 PORTA.3 20p OSCO PORTA.2 PORTA.1 OSCI PORTA.0 20p 19 SH6631A Simplified Custom Code Selection only one switch can be closed ...
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... PORTB 0 15 PORTA 3 14 PORTA 2 PORTA PORTA 0 unit: µ 169.90 624.40 49.90 624.40 -70.10 624.40 624.40 589.25 424.15 304.15 184.15 -409.15 -618.55 -532.40 524.70 -607.40 612.40 -463.40 612.40 -291.20 612.40 -171.20 612.40 -51.20 612.40 68.80 612.40 188.80 529.90 624.40 409.90 624.40 289.90 624.40 SH6631A ...
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... Ordering Information Part No. SH6631AH SH6631A SH6631AM Package Chip Form 20L DIP 20L SOP 21 SH6631A ...
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... E E1 0.250 Typ. (0.262 Max.) 0.100 ± 0.010 e1 0.130 ± 0.010 L α 0° ~ 15° 0.345 ± 0.035 eA S 0.078 Max. 22 unit: inches/ Dimensions in mm 4.45 Max. 0.25 Min. 3.30 ± 0.25 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 26.06 Typ. (26.57 Max.) 7.62 ± 0.25 6.35 Typ. (6.65 Max.) 2.54 ± 0.25 3.30 ± 0.25 0° ~ 15° 8.76 ± 0.89 1.98 Max. SH6631A ...
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... Max. y 0.004 Max. θ 0° ~ 10° is for PC Board surface mount pad pitch design 1 23 unit: inches/ θ L Detail See Detail F Dimensions in mm 2.69 Max. 0.10 Min. 2.33 ± 0.13 0.41 +0.10 -0.05 0.25 +0.10 -0.05 12.80 ± 0.51 7.49 ± 0.25 1.27 ± 0.15 9.50 NOM. 10.31 ± 0.31 0.81 ± 0.20 1.40 ± 0.20 1.07 Max. 0.10 Max. 0° ~ 10° SH6631A ...
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... Data Sheet Revision History Version 2.3 Updated “LPD Circuitry Electrical characteristics” 1.0 Original Content 24 SH6631A Date Sep. 2007 Jul. 1999 ...