vt82c586a ETC-unknow, vt82c586a Datasheet - Page 35

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

Enhanced IDE Controller Registers (Function 1)
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT82C586A. The Bus Master IDE I/O registers are defined
in the SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO
Offset 3-2 - Device ID (0571h=IDE Controller) ............... RO
Offset 5-4 - Command ....................................................... RW
Offset 7-6 - Status ........................................................... RWC
Offset 8 - Revision ID ......................................................... RO
Preliminary Revision 0.1 October 13, 1996
15-10 Reserved
10-9 DEVSEL# Timing ..................default = 01 (medium)
6-0
0-7
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
8
7
Fast Back to Back Cycles ..........fixed at 0 (disabled)
SERR# Enable............................fixed at 0 (disabled)
Address Stepping .......................fixed at 1 (enabled)
Parity Error Response...............fixed at 0 (disabled)
VGA Palette Snoop ....................fixed at 0 (disabled)
Memory Write & Invalidate .....fixed at 0 (disabled)
Special Cycles .............................fixed at 0 (disabled)
Bus Master ............................... default=0 (disabled)
S/G operation can be issued only when the “Bus
Master” bit is enabled.
Memory Space............................fixed at 0 (disabled)
I/O Space
When the “I/O Space” bit is disabled, the device will
not respond to any I/O addresses for both compatible
and native mode.
Detected Parity Error................................ default=0
Signalled System Error.............................. default=0
Received Master Abort.............................. default=0
Received Target Abort .............................. default=0
Signalled Target Abort ..............................Fixed at 0
Data Parity Detected.................................. default=0
Fast Back to Back ......................................Fixed at 1
Reserved
Revision Code for IDE Controller Logic Block

........................................ always reads 0
............................... default=0 (disabled)
........................................ always reads 0
-29-
Offset 9 - Programming Interface ................................... RW
Compatibility Mode (fixed IRQs and I/O addresses):
Native PCI Mode (registers are programmable in I/O space)
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
Offset A - Sub Class Code (01h) ....................................... RO
Offset B - Base Class Code (01h) ...................................... RO
Offset D - Latency Timer (Default=0) ............................. RW
Offset E - Header Type (00h) ............................................ RO
Offset F - BIST (00h) ......................................................... RO
Channel
Channel
6-4
Sec
Sec
7
3
2
1
0
Pri
Pri
Master IDE Capability........... fixed at 1 (Supported)
Reserved
Programmable Indicator - Secondary ...... fixed at 1
Channel Operating Mode - Secondary
The default value for this bit is determined at power-
up as strapped by the SPKR pin
Programmable Indicator - Primary.......... fixed at 1
Channel Operating Mode - Primary
The default value for this bit is determined at power-
up as strapped by the SPKR pin (pin 134)
0
1
0
1
0
1
0
1
Command Block
Command Block
BA @offset 10h
BA @offset 18h
Fixed (mode is determined by bit-2)
Supports both modes (may be set to either
mode by writing bit-2)
Compatibility Mode ............default if SPKR=0
Native PCI Mode ................default if SPKR=1
Fixed (mode is determined by bit-2)
Supports both modes (may be set to either
mode by writing bit-0)
Compatibility Mode.............default if SPKR=0
Native PCI Mode ................default if SPKR=1
Registers
Registers
1F0-1F7
170-177
........................................ always reads 0
BA @offset 1Ch
BA @offset 14h
Control Block
Control Block
Registers
Registers
3F6
376
Register Descriptions
VT82C586A
IRQ
14
15