ch7009b Chrontel, ch7009b Datasheet - Page 5

• Manufacturer Part Number: ch7009b
• Description: Ch7009 Dvi / Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
201-0000-035 Rev 3.31, 11/4/2004
Table 1. Pin Description (continued)
64-Pin
LQFP
43
46
47
48
50 – 55,
58 – 63
57, 56
1, 12, 49
6, 11, 64
45
23, 29
20, 26, 32 3
18, 44
16, 17, 41 3
33
34, 40
# Pins Type
1
1
1
1
12
2
3
3
1
2
2
1
2
In
Out
Out
Out
In / Out
In
Power
Power
Power
Power
Power
Power
Power
Power
Power
Symbol
XO
P-OUT /
TLDET*
BCO/
V SYNC
C/H SYNC
D[11] - D[0]
XCLK,
XCLK*
DVDD
DGND
DVDDV
TVDD
TGND
AVDD
AGND
VDD
GND
Description
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be
attached between this pin and XI / FIN. However, if an external
CMOS clock is attached to XI/FIN, XO should be left open.
Pixel Clock Output / DVI Detect Output
When the CH7009 is operating as a VGA to TV encoder in master
clock mode, this pin provides a pixel clock signal to the VGA
controller which is used as a reference frequency. The output is
selectable between 1X or 2X of the pixel clock frequency. The
output driver is driven from the DVDDV supply. This output has a
programmable tri-state. The capacitive loading on this pin should be
kept to a minimum.
When the CH7009 is operating as a DVI transmitter, this pin
provides an open drain output which pulls low when a termination
change has been detected on the HPDET input. The output is
released through serial port control.
Buffered Clock Output / Vertical Sync Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO reg-
ister.
This pin can also be used as VSYNC output.
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal sync.
The output is driven from the DVDD supply.
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a
graphics controller. The levels are 0 to DVDDV, and the VREF
signal is used as the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the CH7009
for use with the H, V, DE and D[11:0] data. If differential clocks
are not available, the XCLK* input should be connected to
VREF.
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit (in register
1Ch).
Digital Supply Voltage
Digital Ground
I/O Supply Voltage
DVI Transmitter Supply Voltage
DVI Transmitter Ground
PLL Supply Voltage
PLL Ground
DAC Supply Voltage
DAC Ground
(3.3V to 1.1V)
(3.3V-3.6V)
(3.3V-3.6V)
(3.3V-3.6V)
(3.3V-3.6V)
CH7009B
5