ch7005c Chrontel, ch7005c Datasheet - Page 36

• Manufacturer Part Number: ch7005c
• Description: Digital Pc To Tv Encoder With Macrovisiontm
• Manufacturer: Chrontel

CHRONTEL
When the CH7005 is operating in the slave clock mode, the ACIV bit in register 21H should be set to “1” and the
CFRB bit in register 06H should be set to “0”.
*Note: For reduced corss-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0"
Note: P-OUTP (bit 4) is used to invert the P-OUT signal.
Note: DSEN (bit4) controls the BCO / Data Start I/O pin. When this bit is low, the pin continues to operate as the BCO
pin described in the BCO register description. When this bit is high, the pin becomes an input for the Data Start signal.
36
Table 29. FSCI Values (625-Line Modes)
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Mode
13
14
15
19
20
21
25
27
0
1
4
5
8
9
& ACIV = "0".
7
7
“Normal Dot Crawl”
6
6
1,073,747,879
488,262,757*
806,021,060
644,816,848
601,829,058
485,346,014
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
645,499,916
528,951,320
705,268,427
PAL
5
5
4
P-OUTP
R/W
0
4
DSEN
R/W
1
3
FSCI19
R/W
0
3
FSCI15
R/W
0
“Normal Dot Crawl”
651,209,077
520,967,262
392,125,896
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
521,519,134
427,355,957
394,482,422
569,807,942
867,513,766
486,236,111
PAL-N
201-0000-025 Rev. 2.9, 6/24/2004
2
FSCI18
0
2
FSCI14
0
R/W
R/W
Symbol:
Address: 1BH
Bits: 8
Symbol:
Address: 1CH
Bits: 6
1
FSCI17
R/W
0
1
FSCI13
R/W
0
CH7005C
0
FSCI16
R/W
0
0
FSCI12
R/W
0