ch7008a Chrontel, ch7008a Datasheet - Page 30

• Manufacturer Part Number: ch7008a
• Description: Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Register Descriptions (continued)
Power Management Register
This register provides control of the power management functions, a software reset (Reset*) and the SCART output
enable. The CH7008 provides programmable control of its operating states, as described in the table below.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the serial port state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7008 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
Connection Detect Register
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register bits 2-0 are set to 011 (normal mode).
30
Table 19. Power Management
Bit:
Symbol:
Type:
Default:
000
001
010
011
1XX
Bit:
Symbol:
Type:
Default:
PD[2:0]
7
7
Composite Off
Power Down
S-Video Off
Normal (On)
Full Power Down
Operating State
6
6
5
5
CVBS DAC is powered down.
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided outputs).
S-Video DACs are powered down.
All circuits and pins are active.
All circuitry is powered down except serial port interface circuit.
4
SCART
R/W
0
4
3
Reset*
R/W
1
3
YT
R
X
Functional Description
2
PD2
R/W
1
2
CT
R
X
201-0000-027 Rev 2.8, 6/24/2004
Address: 0EH
Bits: 5
Address: 10H
Bits: 4
Symbol: PMR
Symbol: CDR
1
PD1
R/W
0
1
CVBST
R
X
CH7008A
0
PD0
R/W
1
0
SENSE
W
0