em636165 Etron Technology Inc., em636165 Datasheet - Page 17

• Manufacturer Part Number: em636165
• Description: 1m X 16 Bit Synchronous Dram Sdram
• Manufacturer: Etron Technology Inc.

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15 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
17 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
(CKE = "L")
Timing Waveforms)
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
Waveforms, CKE= "H")
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. t
subsequent commands can be issued after one clock cycle from the end of this command.
word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output
buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory
system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every
PDE
(min.) is required when the device exits from the PowerDown mode. Any
17
Rev. 3.4
EM636165
Apr. 2008