ov9625 ETC-unknow, ov9625 Datasheet
ov9625
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ov9625 Summary of contents
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... O mni ision General Description The OV9625 (color) and OV9121 (black and white) are high-performance 1.3 mega-pixel C digital still image and video camera products. Both devices incorporate a 1280 x 1024 (SXGA) image array and an on-chip 10-bit A/D converter capable of operating frames per second (fps) at full resolution and an improved micro lens design to decrease shading ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Functional Description Figure 2 shows the functional block diagram of the OV9625/OV9121 image sensor. The OV9625/OV9121 includes: • Image Sensor Array (1280 x 1024 resolution) • Gain Control • Channel Balance • 10-Bit Analog-to-Digital Converter • Black Level Compensation • ...
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... Black level calibration can be disabled by the user. OV9625/OV9121 allows the user to define window size or region of interest (ROI), as required by the application. Window size setting (in pixels) ranges from 1280 x 1024 (SXGA 640 x 480 (VGA), and can be anywhere inside the 1312 x 1036 boundary ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Sub-sampling Mode Default resolution for the OV9625/OV9121 is 1280 x 1024 pixels, with all active pixels being output (see The OV9625/OV9121 can be programmed to output in 640 x 480 (VGA) sized images for applications where higher resolution image capture is not required. Figure 5 Pixel Array ...
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... Two methods of power-down or standby operation are available with the OV9625/OV9121. • • SCCB Interface RESET pin high and OV9625/OV9121 provides an on-chip SCCB serial control port that allows access to all internal registers, for complete control and monitoring of OV9625/OV9121 operation. Refer to Bus (SCCB) Specification interface. ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Digital Video Port MSB/LSB Swap OV9625/OV9121 has a 10-bit digital video port. The MSB and LSB can be swapped with the control registers. Figure 11 shows some examples of connections with external devices. Figure 11 Connection Examples MSB ...
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... Table 2 Frame and Pixel Rates Frame Rate Adjust OV9625/OV9121 offers three methods of frame rate adjustment. 1. Clock prescaler (see “CLKRC” on page By changing the system clock divide ratio, the frame rate and pixel rate will change together. This method can be used for dividing the frame/pixel rate by: 1/2, 1/3, 1/4 … ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Pin Description Table 3 Pin Description Pin Number Name 01 SVDD 02 VrHIGH 03 NBIT 04 DEVDD 05 DEGND 06 VrLOW 07 PWDN 08 FREX RESET 11 SCCB_E 12 EXPSTB 13 VGA 14 FSIN 15 VcCHG 16 AVDD 17 AGND 18 ASUB 19 VrAD2 20 ADVDD 21 ADGND 22 DVDD 23 DGND Proprietary to OmniVision Technologies ...
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O mni ision Table 3 Pin Description (Continued) Pin Number Name 29 XCLK1 30 XCLK2 31 PCLK DOVDD 38 DOGND 39 HREF 40 CHSYNC 41 VSYNC ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Electrical Characteristics Table 4 Absolute Maximum Ratings Ambient Storage Temperature Supply Voltages (with respect to Ground) All Input/Output Voltages (with respect to Ground) Lead Temperature, Surface-mount process ESD Rating, Human Body model NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage ...
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O mni ision Table 6 AC Characteristics (T Symbol ADC Parameters B Analog bandwidth DLE DC differential linearity error ILE DC integral linearity error Settling time for hardware reset Settling time for software reset Settling time for VGA/XSGA mode change ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Timing Specifications Figure 13 SCCB Timing Diagram SIO_C t SU:STA SIO_D IN SIO_D OUT SCCB_E Table 8 SCCB Timing Specifications Symbol Clock Frequency f SIO_C Clock Low Period t LOW Clock High Period t HIGH SIO_C low to Data Out valid t AA Bus free time before new START ...
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O mni ision Figure 14 SXGA Line/Pixel Output Timing PCLK or MCLK HREF P D[9:0] Figure 15 VGA Line/Pixel Output Timing PCLK or MCLK HREF P D[9:0] Version 1.3, September 15, 2003 dphr ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Figure 16 SXGA Frame Timing VSYNC 4 x tline HREF D[9:0] Invalid Data Figure 17 VGA Frame Timing VSYNC 4 x tline HREF D[9:0] Invalid Data The specifications shown in Table 9 external loading = 30 pF. Table 9 Pixel Timing Specification Symbol t PCLK period p t PCLK rising time ...
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O mni ision Figure 18 Frame Exposure Timing with EXPSTB Staying Low Shutter Open Shutter FREX t line Sensor Sensor Timing Precharge t dfvr VSYNC HREF D[9:0] Row X Figure 19 Frame Exposure Timing with EXPSTB Asserted Shutter Open Shutter ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 OV9625/OV9121 Light Response Figure 20 OV9625/OV9121 Light Response 200 200 180 180 160 160 140 140 120 120 100 100 1.00 1.00 0.90 0.90 0.80 0.80 0.70 0.70 0.60 0.60 0.50 0.50 0.40 0.40 0.30 0.30 0.20 0.20 0.10 0.10 0.00 0.00 Proprietary to OmniVision Technologies 16 C ™ AMERA HIP OV-9620spectrum response Normalized Spectrum Response Wavelength (nm) ...
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... O mni ision Register Set Table 11 provides a list and description of the Device Control registers contained in the OV9625/OV9121. The device slave addresses are 60 for write and 61 for read. Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 00 GAIN 01 BLUE 02 RED 03 COMA ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 09 COMC 0A PIDH 0B PIDL 0C COMD 0D COME Proprietary to OmniVision Technologies 18 C AMERA HIP R/W Common Control C Bit[7:5]: Reserved Bit[4]: Bit[3:2]: Crystal oscillator output current 0C RW Bit[1:0]: Output Drive Select ...
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O mni ision Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 0E COMF 0F COMG 10 AEC Version 1.3, September 15, 2003 R/W Common Control F Bit[7]: System clock selection 0: 1: Bit[6:3]: Reserved Bit[2]: Port ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 11 CLKRC 12 COMH Proprietary to OmniVision Technologies 20 C AMERA HIP R/W Clock Rate Control Bit[7]: Internal PLL ON/OFF selection 0: 1: Bit[6]: Digital video port master/slave selection Bit[5:0]: Clock divider ...
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O mni ision Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 13 COMI 14 COMJ Version 1.3, September 15, 2003 R/W Common Control I Bit[7]: AEC speed selection 0: 1: Bit[6]: AEC speed/step selection 0: 1: ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 15 COMK 16 RSVD 17 HREFST (13 in VGA) 18 HREFEND (63 in VGA) Proprietary to OmniVision Technologies 22 C AMERA HIP R/W Common Control K Bit[7]: Bit[6]: Bit[5]: Bit[4 Bit[3]: Bit[2]: Bit[1]: Bit[0]: XX – ...
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O mni ision Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 19 VSTRT (02 in VGA) 1A VEND (7A in VGA) 1B PSHFT 1C MIDH 1D MIDL 1E-1F RSVD 20 BOFF 21 GbOFF 22 GrOFF Version ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 23 ROFF 24 AEW 25 AEB BBIAS 28 GbBIAS 29 GrBIAS 2A COML Proprietary to OmniVision Technologies 24 C AMERA HIP R/W R Channel Offset Adjustment - auto controlled by internal circuit if COMG[ (see Bit[7 Bit[6:0]: R channel offset adjustment value ...
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O mni ision Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 2B FRARL 2C RBIAS 2D ADDVSL 2E ADDVSH 2F YAVG 30 HSDY 31 HEDY Version 1.3, September 15, 2003 R/W Line Interval Adjustment Value LSB ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 32 COMM (0Ffor VGA) 33 CHLF 34 RSVD 35 VBLM 36 VCHG Proprietary to OmniVision Technologies 26 C AMERA HIP R/W Common Control M Bit[7:6]: Reserved Bit[5]: Bit[4 Bit[3:2]: Horizontal window end position LSBs (MSBs in register ...
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O mni ision Table 11 Device Control Register List Address Register Default (Hex) Name (Hex) 37 ADC 38 ACOM NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Version 1.3, September 15, 2003 R/W ADC ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Package Specifications The OV9625/OV9121 uses a 48-pin ceramic package. Refer to center on the chip. Figure 21 OV9625/OV9121 Package Specifications .560 SQ + .012 / - .005 .430 SQ ± .005 .350 SQ ± .005 42 .032 MIN Pin 1 Index Table 12 OV9625/OV9121 Package Dimensions ...
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... O mni ision Sensor Array Center Figure 22 OV9625/OV9121 Sensor Array Center Package Die Important: Most optical systems invert and mirror the image so the chip is usually mounted on the board with pin 1 (SVDD) down as shown. NOTE: Picture is for reference only, not to scale. Version 1.3, September 15, 2003 ...
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... CMOS SXGA (1.3 MPixel) C OV9625/OV9121 Note: • All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. • OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders) ...