ld7576a Leadtrend Technology, ld7576a Datasheet - Page 11

• Manufacturer Part Number: ld7576a
• Description: Green-mode Pwm Controller With High-voltage Start-up Circuit And Adjustable Olp Delay Time
• Manufacturer: Leadtrend Technology

Oscillator and Switching Frequency
The switching frequency of LD7576A is fixed at 65KHz
internally
consideration of the EMI performance, thermal treatment,
component sizes and transformer design.
Internal Slope Compensation
A fundamental issue of current mode control is the stability
problem when its duty-cycle is more than 50%. To stabilize
the control loop, slope compensation is needed in the
traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In
LD7576A, the internal slope compensation circuit has
been implemented to simplify the external circuit design.
On/Off Control
By pulling COMP pin lower than 1.2V will disable the gate
output pin of LD7576A immediately. The off mode can be
released when the pull-low signal is removed.
Leadtrend Technology Corporation
LD7576A-DS-00b November, 2009
to
provide
Fig. 16
the
optimized
www.leadtrend.com.tw
operations
in
11
Dual-Oscillator Green-Mode Operation
There
implemented in different chips for the green-mode or
power saving requirements such as “burst-mode control”,
“skipping-cycle mode”, “variable off-time control “…etc.
The basic operation theory of all these approaches
intended to reduce the switching cycles under light-load or
no-load condition either by skipping some switching pulses
or reduce the switching frequency.
By using LD proprietary dual-oscillator technique, the
green-mode frequency can be well controlled to avoid the
generation of audible noise.
Over Load Protection (OLP) - Auto Recovery
To protect the circuit from being damaged during over load
condition and short or open loop condition, the LD7576A is
implemented with smart OLP function. LD7576A features
auto recovery function, the waveform of which is
exemplified in figure 17. In the example of the fault
condition, the feedback system tends to force the voltage
loop toward the saturation and then pull the voltage high
on COMP pin (VCOMP). When the V
the OLP threshold of 5V and stays for longer than the OLP
delay time, the protection will be activated to turn off the
gate output and to stop the switching of power circuit. The
OLP delay time, set by the capacitor connected to CT pin,
is to prevent the false triggering from the power-on and
turn-off transient. The higher capacitance of the capacitor
in CT pin, the longer OLP delay time. The recommended
capacitance will be 0.1μF for a OLP delay time around
110mS and 0.047μF for around 45mS.
A divide-by-2 counter is implemented to reduce the
average power under OLP behavior. Whenever OLP is
activated, the output is latched off and the divide-by-2
counter starts to count the number Vcc reaches UVLO(off).
The latch will be released when Vcc reaches the 2nd time
and then the output is recovered to switching again.
With the protection mechanism, the average input power
will be minimized, so that the component temperature and
stress can be controlled within a safe operating area.
are
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different
LD7576A
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