ld7575b Leadtrend Technology, ld7575b Datasheet - Page 11

• Manufacturer Part Number: ld7575b
• Description: Green-mode Pwm Controller With High-voltage Start-up Circuit
• Manufacturer: Leadtrend Technology

OVP (Over Voltage Protection) on Vcc
The Vgs ratings of the nowadays power MOSFETs are most
with maximum 30V. To prevent the Vgs from the fault
condition, LD7575B is implemented an OVP function on Vcc.
Whenever the Vcc voltage is higher than the OVP threshold
voltage, the output gate drive circuit will be shutdown
simultaneous thus to stop the switching of the power
MOSFET until the next UVLO(on).
The Vcc OVP function in LD7575B is an auto-recovery type
protection. If the OVP condition, usually caused by the
feedback loop opened, is not released, the Vcc will tripped
the OVP level again and re-shutdown the output. The Vcc
is working as a hiccup mode.
operation.
On the other hand, if the OVP condition is removed, the Vcc
level will get back to normal level and the output is
automatically returned to the normal operation.
Leadtrend Technology Corporation
LD7575B-DS-00 May 2008
UVLO(off)
UVLO(on)
5.0V
VCC
COMP
OUT
Switching
30mS
OLP
Non-Switching
OLP Counter Reset
Fig. 17
2nd UVLO(off)
OLP trip Level
Figure 18 shows its
Switching
t
t
t
11
Fault Protection
A lot of protection features have been implemented in the
LD7575B to prevent the power supply or adapter from being
damaged caused by single fault condition on the open or
short condition on the pin of LD7575B. Under the conditions
listed below, the gate output will be off immediately to
protect the power circuit ---
Pull-Low Resistor on the Gate Pin of MOSFET
In LD7575B, an anti-floating resistor is implemented on the
OUT pin to prevent the output from any uncertain state
which may causes the MOSFET working abnormally or false
triggered-on.
condition of disconnection of gate resistor Rg thus it is still
strongly recommended to have a resistor connected on the
MOSFET gate terminal (as shown in figure 19) to provide
extra protection for fault condition.
This external pull-low resistor is to prevent the MOSFET
from damage during power-on under the gate resistor is
disconnected. In such single-fault condition, as show in
figure 20, the resistor R8 can provide a discharge path to
avoid the MOSFET from being false-triggered by the current
through the gate-to-drain capacitor Cgd.
MOSFET is always pull-low and kept in the off-state
whenever the gate resistor is disconnected or opened in any
case.
RT pin short to ground
RT pin floating
CS pin floating
However, such design won’t cover the
Fig. 18
LD7575B
Therefore, the