ld7577gs Leadtrend Technology, ld7577gs Datasheet - Page 11

• Manufacturer Part Number: ld7577gs
• Description: High Voltage Green-mode Pwm Controller With Brown-out Protection
• Manufacturer: Leadtrend Technology

Oscillator and Switching Frequency
The switching frequency of the LD7577 is fixed as 65KHz
internally to provide the optimized operations by considering
the EMI performance, thermal treatment, component sizes
and transformer design.
Internal Slope Compensation
Stability is crucial for current mode control when it operates
at more than 50% of duty-cycle. To stabilize the control loop,
the slope compensation is required in the traditional
UC384X design by injecting the ramp signal from the RT/CT
pin through a coupling capacitor. In the LD7577, the internal
slope compensation circuit has been implemented to
simplify the external circuit design.
On/Off Control
Pulling COMP pin below 1.2V will turn off the LD7577 and
disable the gate output pin of the LD7577. The off-mode will
be released when the pull-low signal at COMP pin is
removed.
Leadtrend Technology Corporation
LD7577-DS-01 January 2009
Fig. 16
www.leadtrend.com.tw
11
Dual-Oscillator Green-Mode Operation
Lots of topologies have been implemented in different chips
for the green-mode or power saving requirements such as
“burst-mode control”, “skipping-cycle mode”, “variable
off-time control “…etc. The basic operation theory of all
these approaches intends to reduce the switching cycles
under light-load or no-load condition either by skipping some
switching pulses or by reducing the switching frequency.
What the LD7577 uses to implement the power-saving
operation is Leadtrend Technology’s own IP. By using this
dual-oscillator control, the burst -mode frequency can be
well controlled and further to avoid the generation of audible
noise.
Over Load Protection (OLP)
To protect the circuit from being damaged under over load
condition or short condition, a smart OLP function is built in
with the LD7577, as shown in Figure 17 shows the
waveforms of the OLP operation. If output voltage drops,
the feedback system tends to force the voltage loop toward
the saturation (6V) and then pulls the voltage of COMP pin
to high. Whenever the V
5.0V and continues over 30mS, OLP is activated and then
turns off the gate output to stop the switching of power
circuit. The 30mS delay time is to prevent the false trigger
from the power-on and turn-off transient.
A divide-2 counter is implemented to reduce the input
average power under OLP behavior.
activated, the output is latched off and the divide-2 counter
starts to count the number of UVLO(off).
released if the 2nd UVLO(off) point is counted then the
power circuit is recovered to switch again.
By using such protection mechanism, the average input
power can be reduced to a very low level so that the
component temperature and stress can be controlled within
the safe operating area.
COMP
trips to the OLP threshold
LD7577
Whenever OLP is
The latch is