az100lvel16vr Arizona Microtek, Inc., az100lvel16vr Datasheet - Page 4

• Manufacturer Part Number: az100lvel16vr
• Description: Ecl/pecl Oscillator Gain Stage & Buffer With Selectable Enable
• Manufacturer: Arizona Microtek, Inc.

AZ100LVEL16VR
MLP 8, 2x2 mm Package (VRNE)
(NC), the Q ¯ and Q
HG
to V
connected directly to V
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
May 2008 * REV - 17
output is forced low while Q ¯ continues to follow the data input. The Q ¯ output has an internal 4 mA current source
A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open
EE
The data input D is tied to the V
V
EN
, in most cases eliminating the need for an external pull-down resistor.
Q
Q
Q
D
EN
BB
D
Q
HG
HG
470
HG
AZ100LVEL16VRNE
/Q ¯
BB
HG
. Bypassing V
outputs follow the data input. When EN is LOW, the Q
TIMING DIAGRAM
4mA
BB
BB
pin through a 470 Ω internal bias resistor while the inverting input D ¯ is
to ground with a 0.01 μF capacitor is recommended.
www.azmicrotek.com
(CMOS Input
Levels)
Q
Q
V
4
HG
HG
EE
D
Q ¯
Q
V
EN
V
V
HG
BB
EE
CC
/Q ¯
PIN
HG
V
V
EN
BB
EE
D
PIN DESCRIPTION
Data Input
Data Output
Data Outputs w/High Gain
Reference Voltage Output
Enable Input
Negative Supply
Positive Supply
1
3
4
2
AZ100LVEL16VRNE
HG
MLP 8, 2x2 mm
output is forced high and the Q ¯
TOP VIEW
Leave Pad
connect to
FUNCTION
open or
V
EE
8
7
6
5
Q
Q
V
Q
CC
HG
HG