DS1010-175 DALLAS [Dallas Semiconductor], DS1010-175 Datasheet - Page 6

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DS1010-175

Manufacturer Part Number
DS1010-175
Description
10-Tap Silicon Delay Line
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1010.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (V
Input Pulse:
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level
on the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
CC
):
5.0V ± 0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
3.0 ns max.
500 ns (1 µs for -500)
1 µs ( 2 µs for -500)
25°C ± 3°C
50 ohm max.
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DS1010

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