DS1020-50 DALLAS [Dallas Semiconductor], DS1020-50 Datasheet
DS1020-50
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DS1020-50 Summary of contents
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FEATURES All-silicon time delay Models with 0.25 ns and 0.5 ns steps Programmable using 3-wire serial port or 8- bit parallel port Leading and trailing edge accuracy Economical Auto-insertable, low profile, 16-pin SOIC package Low-power CMOS TTL/CMOS-compatible Vapor phase, ...
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PARALLEL MODE ( the PARALLEL programming mode, the output of the DS1021 will reproduce the logic state of the input after a delay determined by the state of the 8 program input pins P0 - P7. The ...
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FUNCTION BLOCK DIAGRAM Figure 1 SERIAL READOUT Figure 2 DS1021 ...
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... CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 3 PART NUMBER TABLE Table 1 PART NUMBER STEP ZERO DELAY TIME DS1020-25 10 ± 2 DS1020-50 10 ± 2 DELAY VS. PROGRAMMED VALUE Table 2 BINARY 0 PROGRAMMED 0 VALUE PART 0 NUMBER 0 DS1021-25 10.00 DS1021-50 10.0 All delays in nanoseconds, referenced to input pin. DS1021 DS1021 ...
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DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 4 TEST SETUP DESCRIPTION Figure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1021. The input waveform is produced by a precision pulse generator under software control. Time delays are ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current * This is a stress rating only and functional operation of the device at these or any other conditions above ...
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PARAMETER SYMBOL Parallel Input Change to Delay Invalid Enable to Delay Valid Enable to Delay Invalid V Valid to Device CC Functional V Rise Time CC Input Pulse Width Input to Output Delay Input Period CAPACITANCE PARAMETER SYMBOL Input ...
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TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the t ...
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TIMING DIAGRAM: SERIAL MODE ( Figure 8 TIMING DIAGRAM: POWER-UP Figure 9 NOTES: 1. All voltages are referenced to ground and 25°C. Delay accurate on both rising and falling edges within tolerances given ...