DS1075-100 DALLAS [Dallas Semiconductor], DS1075-100 Datasheet
DS1075-100
Related parts for DS1075-100
DS1075-100 Summary of contents
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... The DS1075 is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily, economically and using minimal board area. EconOscillator/Divider PIN ASSIGNMENT 1 I/O 2 OUT0 GND DS1075Z 150-MIL SOIC DS1075M 300-MIL DIP FREQUENCY OPTIONS Part No. DS1075-100 DS1075-80 DS1075-66 DS1075- DS1075 8 OSCIN 7 XTAL 6 OE PDN/SELX 5 Max O/P freq. 100.000 MHz 80.000 MHz 66 ...
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BLOCK DIAGRAM Figure 1 PART INTOSC NO. FREQUENCY SUFFIX -100 100.000 MHz 080 80.000 MHz -66 66.667 MHz -60 60.000 MHz ...
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... If a crystal is not used this pin should be left open. Output Enable Function (OE pin): The DS1075 also features a “synchronous” output enable. When high logic level the oscillator free runs. When this pin is taken low OUT is held low, immediately if OUT is already low it’ ...
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The register settings are nonvolatile, the values being stored automatically in EEPROM when the registers are programmed. Note: The register bits cannot be used to make mode or frequency changes on the fly. ...
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Table 2 DIV1 E/ I MSEL BIT BIT* BIT *Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the ...
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... Since the output enable, internal master oscillator and/or external master oscillator are likely all asynchronous there is the possibility of timing difficulties in the application. difficulties the DS1075 features an “enabling sequencer” to produce predictable results when the device is enabled and disabled. In particular the output gating is configured so that truncated output pulses can never be produced ...
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Figure 5 Figure 6 SELECT TIMING If the PDN bit is set to “0”, the an externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs in a glitch-free fashion. Two asynchronous clock signals are involved, ...
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Figure 7 Depending on the relative timing of the cycle the output after the falling edge of I pulses will be dependent on the relative timing between t edge of and the first rising edge of the ...
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SELX and the first rising edge of the externally derived clock is t SIE . Approximate maximum and minimum values of these parameters are: t (min LOW I t (max ...
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Figure 9 POWER-ON RESET When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar to that which occurs when the device is restored from a power-down condition. This sequence comprises two stages, first ...
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... The hardware configuration is shown in the diagram. A bus master is used to read and write data to the DS1075’s internal registers. The bus master may have either an open-drain or TTL-type architecture. Figure 11 Programming mode is entered by simply powering up the DS1075 with a pull-up of approximately 5KW. This will pull the IN/OUT pin above V DS1075 to internally release the IN/OUT pin (after t the supply rail and await the Master Tx Reset pulse (see diagram) ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the DS1075. The presence pulse lets the bus master know that the DS1075 is present and is ready to operate. Figure 13 FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four function commands ...
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... DS1075. During write time slots, the delay circuit determines when the DS1075 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS1075 will hold the data line low overriding the 1 generated by the master. If the data bit is a “ ...
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... IN/OUT pin is removed, normal device operation will be restored next time power is applied. DEFAULT REGISTER VALUES Unless ordered from the factory with specific register program values, the DS1075 is shipped with the following default register values: DIV = 0 0000 0000 (Programmable divider will divide by two) ...
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... OE, IN/OUT)(OSCIN) High-level Input Current ( / , OE, PDN SELX IN/OUT)(OSCIN) Low-level Input Current ( / , OE, PDN SELX IN/OUT)(OSCIN) Supply Current (Active) DS1075-100 DS1075-80 DS1075-66 DS1075-60 Standby Current (power-down) -1.0V to +7.0V 0°C to 70°C -55°C to +125°C 260°C for 10 seconds (T CONDITION mA, ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Output Frequency Tolerance Combined Freq. Variation Long Term Stability Maximum Input Frequency Minimum Output Frequency Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ OUT Hi-Z from PDN ↓ OUT0 Hi-Z from ...
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AC ELECTRICAL CHARACTERISTICS - CALCULATED PARAMETERS The following characteristic are derived from various device operating parameters (frequency, mode etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount ...
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... Please review this summary carefully. 1. Page 1, description, second paragraph. Word change 2. Page 14, AC electrical characteristic. Add Long Term Stability and new spec. The following represent the key differences between 05/01/97 and 10/15/97 version of the DS1075 data sheet. Please review this summary carefully. 1. Status Change (REMOVE PRELIMINARY). ...