DS24B33+ MAXIM [Maxim Integrated Products], DS24B33+ Datasheet - Page 17

• Manufacturer Part Number: DS24B33+
• Description: 4Kb 1-Wire EEPROM with 200k Write/Erase Cycles
• Manufacturer: MAXIM [Maxim Integrated Products]

The DS24B33 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and pres-
ence pulse, write-zero, write-one, and read-data.
Except for the presence pulse, the bus master initiates
all falling edges. The DS24B33 can communicate at
two different speeds: standard speed and overdrive
speed. If not explicitly set into the overdrive mode, the
DS24B33 communicates at standard speed. While in
overdrive mode the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
from active to idle, the voltage needs to rise from
V
voltage to make this rise is seen in Figure 10 as ε, and
its duration depends on the pullup resistor (R
and the capacitance of the 1-Wire network attached.
The voltage V
determining a logical level, not triggering any events.
Figure 10 shows the initialization sequence required to
begin any communication with the DS24B33. A reset
pulse followed by a presence pulse indicates that the
DS24B33 is ready to receive data, given the correct
ROM and memory function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for t
A t
mode, returning the device to standard speed. If the
DS24B33 is in overdrive mode and t
than 80µs, the device remains in overdrive mode. If the
device is in overdrive mode and t
and 480µs, the device resets, but the communication
speed is undetermined.
Figure 10. Initialization Procedure: Reset and Presence Pulse
ILMAX
RSTL
past the threshold V
duration of 480µs or longer exits the overdrive
V
IHMASTER
V
ILMAX
V
ILMAX
V
PUP
V
0V
TH
TL
RSTL
______________________________________________________________________________________
PUP
is relevant for the DS24B33 when
+ t
below the threshold V
t
F
F
to compensate for the edge.
MASTER Tx "RESET PULSE"
TH
1-Wire Signaling
RESISTOR
. The time it takes for the
RSTL
RSTL
is between 80µs
t
RSTL
is no longer
PUP
TL
. To get
) used
4Kb 1-Wire EEPROM with
200k Write/Erase Cycles
ε
MASTER
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to V
through the pullup resistor, or in case of a DS2482-x00
or DS2480B driver, by active circuitry. When the thresh-
old V
then transmits a presence pulse by pulling the line low
for t
test the logical state of the 1-Wire line at t
The t
t
expired, the DS24B33 is ready for data communication.
In a mixed population network, t
ed to minimum 480µs at standard speed and 48µs at
overdrive speed to accommodate other 1-Wire devices.
Data communication with the DS24B33 takes place in
time slots, which carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
For a write-one time slot, the voltage on the data line
must have crossed the V
one low time t
slot, the voltage on the data line must stay below the
V
expired. For the most reliable communication, the
PDLMAX
TH
t
PDH
PDL
threshold until the write-zero low time t
RSTH
TH
t
MSP
. To detect a presence pulse, the master must
is crossed, the DS24B33 waits for t
, and t
MASTER Rx "PRESENCE PULSE"
window must be at least the sum of t
t
PDL
W1LMAX
t
RSTH
RECMIN
TL
is expired. For a write-zero time
, the DS24B33 starts its internal
. Immediately after t
TH
t
REC
Read/Write Time Slots
DS24B33
threshold before the write-
RSTH
should be extend-
Master-to-Slave
MSP
.
W0LMIN
PDH
PDHMAX
RSTH
and
PUP
17
is
is
,