UPD70433GD-16-5BB NEC [NEC], UPD70433GD-16-5BB Datasheet - Page 133

• Manufacturer Part Number: UPD70433GD-16-5BB
• Description: V55PITM 16-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

Remark
ASTB delay time from RD , IORD
RD , IORD delay time from WRL , WRH , IOWR
DEX delay time from CLKOUT
DEX hold time (from CLKOUT )
Data input setup time (to CLKOUT )
Data input hold time (from CLKOUT )
WR delay time from CLKOUT
WR delay time from CLKOUT
WR low-level width
Data output delay time from CLKOUT
Data output hold time (from CLKOUT )
ASTB delay time from WR
RAS delay time from CLKOUT
RAS delay time from CLKOUT
RAS high-level width
RAS delay time from WRH , WRL
Address setup time (to RAS )
READY setup time (to CLKOUT )
READY hold time (from CLKOUT )
READY setup time (to CLKOUT )
READY hold time (from CLKOUT )
RESET low-level width
NMI high-level width
NMI low-level width
INTPm setup time (to CLKOUT )
INTPm high-level width
INTPm low-level width
POLL setup time (to CLKOUT )
HLDRQ setup time (to CLKOUT )
HLDAK delay time from CLKOUT
HLDAK delay time from bus float
Bus output delay time from HLDAK
n : Number of address wait states
N : Number of data wait states
T : t
CYK
Numbers in the Symbol column correspond to numbers in the timing charts.
PARAMETER
119
120
121
122
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DRSTH
DWRH
DKDX
HKDX
SDK
HKDR
DKWL
DKWH
WWL
DKD
HKDW
DWSTH
DKRAL
DKRAH
WRAH
DWRAH
SARAL
SRYHK
HKRYL
SRYLK
HKRYH
WRSL1
WRSL2
WNIH
WNIL
SIQK
WIQH
WIQL
SPLK
SHQK
DKHA
FCHA
DHAC
STOP release/power-on reset
System reset
m = 0 to 5
m = 0 to 5
m = 0 to 5
TEST CONDITIONS
(N + 1)T – 12
(N + 0.5)T – 10
(n + 1)T – 15
1000 + 2T
T – 22.5
nT – 12
MIN.
10T
10T
nT
11
18
12
18
12
30
25
25
25
0
0
0
0
0
0
0
3
0
0
0
5
5
0
0
nT + 22
MAX.
27
22
22
27
22
27
PD70433
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
133