DS1386 DALLAS [Dallas Semiconductor], DS1386 Datasheet - Page 3

• Manufacturer Part Number: DS1386
• Description: RAMified Watchdog Timekeeper
• Manufacturer: DALLAS [Dallas Semiconductor]

PACKAGES
The DS1386 is available in two packages (32-pin DIP module and 34-pin PowerCap module). The 32-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1386P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
OPERATION - READ REGISTERS
The DS1386 executes a read cycle whenever
and
defines which of the registers is to be accessed. Valid data will be available to the eight data output
drivers within t
access times are also satisfied. If
measured from the latter occurring signal (
t
OPERATION - WRITE REGISTERS
The DS1386 is in the write mode whenever the
the active (Low) state after the address inputs are stable. The latter occurring falling edge of
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of
or
for a minimum recovery state (t
bus with sufficient Data Set-Up (t
contention. However, if the output bus has been enabled (
outputs in t
DATA RETENTION
The RAMified Timekeeper provides full functional capability when V
write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of V
any additional support circuitry. The DS1386 constantly monitors V
the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become
“don’t care.” The two interrupts
regardless of the level of V
interrupt pins are never pulled up to a value that is greater than V
approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain
the clock and timer data and functionality. It is also required to insure that during this time (battery
backup mode), the voltage present at
when V
disconnects the internal lithium energy source. Normal operation can resume after V
for a period of 200 ms.
CE
OE
WE
for
OE
or
. All address inputs must be kept valid throughout the write cycle.
OE
CC
WE
(Output Enable) are active (Low). The unique address specified by the address inputs (A0-A14)
rather than address access.
ODW
rises above approximately 3.0 volts, the power switching circuit connects external V
. The
ACC
from its falling edge.
OE
(Access Time) after the last address-input signal is stable, providing that
control signal should be kept inactive (High) during write cycles to avoid bus
CC
. However, it is important to insure that the pull-up resistors used with the
WR
INTA
DS
) before another cycle can be initiated. Data must be valid on the data
OE
) and Data Hold Time (t
and
and
INTA
INTB
CE
CE
and
WE
or
access times are not satisfied, then data access must be
WE
(INTB) and the internal clock and timers continue to run
3 of 20
OE
INTB
(Write Enable) is inactive (High),
(Write Enable) and
) and the limiting parameter is either t
(INTB) never exceeds 3.0V. During power-up,
CE
DH
and
) with respect to the earlier rising edge of
OE
CC
. Should the supply voltage decay,
active), then
CC
CC
CE
WE
+ 0.3V. As V
is greater than 4.5 volts and
(Chip Enable) signals are in
must return to the high state
CC
WE
CE
exceeds 4.5 volts
will disable the
CC
(Chip Enable)
CO
CE
falls below
CE
CC
for
and
without
or
CC
CE
WE
and
OE
CE
or