DS1388Z-3 MAXIM [Maxim Integrated Products], DS1388Z-3 Datasheet - Page 15

• Manufacturer Part Number: DS1388Z-3
• Description: I2C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROM
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 7. I
SDA
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and the
STOP conditions is not limited, and is determined by
the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) after the reception of each byte. The master
device must generate an extra clock pulse, which is
associated with this acknowledge bit. The DS1388
does not generate any acknowledge bits if access to
the EEPROM is attempted during an internal pro-
gramming cycle.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by generating a not-acknowledge (NACK) bit on
the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
SCL
CONDITION
START
2
C Data Transfer Overview
MSB
I
1
2
C RTC/Supervisor with Trickle Charger
2
SLAVE ADDRESS
6
____________________________________________________________________
7
DIRECTION
R/W
BIT
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
ACK
9
and 512 Bytes EEPROM
Figures 8 and 9 detail how data transfer is accom-
plished on the I
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data are transferred with the
most significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a NACK is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeat-
ed START condition. Since a repeated START
condition is also the beginning of the next serial
transfer, the bus is not released. Data are transferred
with the most significant bit (MSB) first.
1
2
REPEATED IF MORE BYTES
2
C bus. Depending upon the state of
ARE TRANSFERED
3–7
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
ACK
9
OR REPEATED
CONDITION
CONDITION
START
STOP
15