DS14285-DS14287 DALLAS [Dallas Semiconductor], DS14285-DS14287 Datasheet - Page 15

• Manufacturer Part Number: DS14285-DS14287
• Description: Real Time Clock with NV RAM Control
• Manufacturer: DALLAS [Dallas Semiconductor]

PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2
UPDATE CYCLE
The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and
alarm bytes is frozen and will not update as the time increments. However, the time countdown chain
continues to update the internal copy of the buffer. This feature allows time to maintain accuracy
independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and
calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 s later. If a low is read on the UIP bit, the user has at least 244 s before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 s.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts
that occur at a rate of greater than t
occurrence of the periodic interrupt. The reads should be complete within 1 (t
data is not read during the update cycle.
RS3
SELECT BITS REGISTER A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BUC
allow valid time and date information to be reached at each
INTERRUPT RATE
t
PI
1.953125 ms
976.5625 s
3.90625 ms
3.90625 ms
122.070 s
244.141 s
488.281 s
7.8125 ms
7.8125 ms
15.625 ms
PERIODIC
31.25 ms
15 of 25
62.5 ms
125 ms
250 ms
500 ms
None
PI/
SQW OUTPUT
FREQUENCY
2
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
+ t
256 Hz
128 Hz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
None
8 Hz
4 Hz
2 Hz
BUC
DS14285/DS14287
) to ensure that