DS90CF583MTD NSC [National Semiconductor], DS90CF583MTD Datasheet
DS90CF583MTD
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DS90CF583MTD Summary of contents
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... LCD panel controllers. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Block Diagrams Order Number DS90CF583MTD See NS Package Number MTD56 TRI-STATE ® registered trademark of National Semiconductor Corporation. ...
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Block Diagrams (Continued) www.national.com DS012616-2 2 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. LVDS Receiver ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current, CCTZ Power Down RECEIVER SUPPLY CURRENT I Receiver Supply Current, CCRW Worst Case I Receiver Supply Current, CCRG 16 ...
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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol CLHT CMOS/TTL Low-to-High Transition Time ( Figure 4 ) CMOS/TTL High-to-Low Transition Time ( Figure 4 ) CHLT RCOP RxCLK OUT Period RCOH RxCLK OUT High ...
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AC Timing Diagrams (Continued) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. ...
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AC Timing Diagrams (Continued) FIGURE 5. DS90CF583 (Transmitter) Input Clock Transition Time Note:Measurements at Vdiff = 0V Note: TCSS measured between earliest and latest LVDS edges. Note: TxCLK Differential High Low Edge FIGURE 6. DS90CF583 (Transmitter) Channel-to-Channel Skew and Pulse ...
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AC Timing Diagrams (Continued) FIGURE 9. DS90CF583 (Transmitter) Clock In to Clock Out Delay FIGURE 10. DS90CF584 (Receiver) Clock In to Clock Out Delay FIGURE 11. DS90CF583 (Transmitter) Phase Lock Loop Set Time FIGURE 12. DS90CF584 (Receiver) Phase Lock Loop ...
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AC Timing Diagrams (Continued) FIGURE 13. Receiver LVDS Input Pulse Position Measurement SW — Setup and Hold Time (Internal Data Sampling Window) TCCS — Transmitter Output Skew RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) Cable ...
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AC Timing Diagrams (Continued) FIGURE 16. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583) DS90CF583 Pin Descriptions — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, ...
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DS90CF583 Pin Descriptions — FPD Link Transmitter Pin Name I/O No. GND I 5 Ground pins for TTL inputs PLL Power supply pin for PLL CC PLL GND I 2 Ground pins for PLL LVDS V I ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF583MTD or DS90CF584MTD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION ...